JPS54145444A - Control system of buffer memory - Google Patents

Control system of buffer memory

Info

Publication number
JPS54145444A
JPS54145444A JP5432478A JP5432478A JPS54145444A JP S54145444 A JPS54145444 A JP S54145444A JP 5432478 A JP5432478 A JP 5432478A JP 5432478 A JP5432478 A JP 5432478A JP S54145444 A JPS54145444 A JP S54145444A
Authority
JP
Japan
Prior art keywords
memory
address
data
counter
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5432478A
Other languages
Japanese (ja)
Other versions
JPS5919376B2 (en
Inventor
Kazunori Demachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53054324A priority Critical patent/JPS5919376B2/en
Publication of JPS54145444A publication Critical patent/JPS54145444A/en
Publication of JPS5919376B2 publication Critical patent/JPS5919376B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To simplify the control of a memory method and to reduce its cost by providing an empty memory which is stored with information on an address, where a buffer memory writes data, by receiving a command from an address counter. CONSTITUTION:On a write cycle, a write cycle command is inputted to empty memory 5 and at the same time, a write cycle clock is supplied to buffer memory 1, memory 5 and address counter 2. As a result, FF6 is reset. Simultaneously, an address signal is sent from counter 2 to memories 1 and 5, input data are written to memory 1 in sequence, and memory 5 is stored with information on an address where a write to memory 1 ends. On a read cycle, next, a read cycle clock is sent to counter 2, which reads out data from memory 1 at every time of counting up. At the same time, the data are outputted to memory 5 as well and after the final data are read out, FF6 is reset by the output of memory 5, so that the command for the read cycle end will be sent out.
JP53054324A 1978-05-08 1978-05-08 Buffer memory control method Expired JPS5919376B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53054324A JPS5919376B2 (en) 1978-05-08 1978-05-08 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53054324A JPS5919376B2 (en) 1978-05-08 1978-05-08 Buffer memory control method

Publications (2)

Publication Number Publication Date
JPS54145444A true JPS54145444A (en) 1979-11-13
JPS5919376B2 JPS5919376B2 (en) 1984-05-04

Family

ID=12967398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53054324A Expired JPS5919376B2 (en) 1978-05-08 1978-05-08 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS5919376B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57169842A (en) * 1981-04-13 1982-10-19 Fuji Electric Co Ltd Data receiver
JPS59231955A (en) * 1983-06-15 1984-12-26 Nec Corp Signal transmission circuit
JPS62209612A (en) * 1986-02-14 1987-09-14 Fujitsu Ltd Detecting circuit for buffer overflow

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57169842A (en) * 1981-04-13 1982-10-19 Fuji Electric Co Ltd Data receiver
JPS59231955A (en) * 1983-06-15 1984-12-26 Nec Corp Signal transmission circuit
JPS62209612A (en) * 1986-02-14 1987-09-14 Fujitsu Ltd Detecting circuit for buffer overflow

Also Published As

Publication number Publication date
JPS5919376B2 (en) 1984-05-04

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