JPS5693191A - Memory error correction and automatic diagnosis system - Google Patents
Memory error correction and automatic diagnosis systemInfo
- Publication number
- JPS5693191A JPS5693191A JP16859179A JP16859179A JPS5693191A JP S5693191 A JPS5693191 A JP S5693191A JP 16859179 A JP16859179 A JP 16859179A JP 16859179 A JP16859179 A JP 16859179A JP S5693191 A JPS5693191 A JP S5693191A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- register
- error
- writing
- bit error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To secure an effective correction at a multiplex bit error detection as well as a detection for the position of a faulty memory cell, by writing a fixed pattern into the address of a memory where the multiplex bit error is caused.
CONSTITUTION: A normal writing data is written into the memory 2 via the self- diagnosis control circuit 6 and the writing register 1. The reading data of the memory 2 is set to the reading register 3 via the input control circuit 11 and then checked by the ECC circuit 4. The patterns of all "0" and all "1" are written to the address of the memory 2 where an error is caused when the multiplex bit error is detected. Each of these patterns which is read out and inverted 23 and the contents of the register 3 are applied to exclusive logic sum 10 to correct the fixed faulst. At the same time, the position of the error bit is detected 4 to be informed to outside via the normal made/self-diagnosis mode switching circuit 5.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16859179A JPS5693191A (en) | 1979-12-25 | 1979-12-25 | Memory error correction and automatic diagnosis system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16859179A JPS5693191A (en) | 1979-12-25 | 1979-12-25 | Memory error correction and automatic diagnosis system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5693191A true JPS5693191A (en) | 1981-07-28 |
Family
ID=15870887
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16859179A Pending JPS5693191A (en) | 1979-12-25 | 1979-12-25 | Memory error correction and automatic diagnosis system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5693191A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8607120B2 (en) | 2009-03-19 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor memory device for performing additional ECC correction according to cell pattern and electronic system including the same |
-
1979
- 1979-12-25 JP JP16859179A patent/JPS5693191A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8607120B2 (en) | 2009-03-19 | 2013-12-10 | Samsung Electronics Co., Ltd. | Semiconductor memory device for performing additional ECC correction according to cell pattern and electronic system including the same |
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