JPS5638636A - Data processing unit - Google Patents

Data processing unit

Info

Publication number
JPS5638636A
JPS5638636A JP11418779A JP11418779A JPS5638636A JP S5638636 A JPS5638636 A JP S5638636A JP 11418779 A JP11418779 A JP 11418779A JP 11418779 A JP11418779 A JP 11418779A JP S5638636 A JPS5638636 A JP S5638636A
Authority
JP
Japan
Prior art keywords
address
incorrect
odd number
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11418779A
Other languages
Japanese (ja)
Other versions
JPS6218943B2 (en
Inventor
Kenichiro Oda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11418779A priority Critical patent/JPS5638636A/en
Publication of JPS5638636A publication Critical patent/JPS5638636A/en
Publication of JPS6218943B2 publication Critical patent/JPS6218943B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)
  • Storage Device Security (AREA)

Abstract

PURPOSE: To make ease of maintenance, by judging the failure of element or incorrect address designation to the memory error in the data processor accessed in common with a plurality of devices and storing the line address and incorrect address at that time.
CONSTITUTION: ROMs 4, 5, 6 have an odd number parity 1 bit, and the data of an odd number parity is written in the correct address and the pattern data which can be discriminated as correct address is written in the incorrect (underfined area) address. When the line address is scanned, the IF control word 1 is read out to the work register 2 to cause the input address 23 and the enable signal 24 of ROM through the modification at the interface common controlling circuit 3. The odd number parity check is made for the data read out from ROM at the circuit 7 and the nonpropriety pattern is checked at the circuit 8, and output is produced to the gate 42 in case of the failure of element and to the gate 43 if incorrect address designation.
COPYRIGHT: (C)1981,JPO&Japio
JP11418779A 1979-09-07 1979-09-07 Data processing unit Granted JPS5638636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11418779A JPS5638636A (en) 1979-09-07 1979-09-07 Data processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11418779A JPS5638636A (en) 1979-09-07 1979-09-07 Data processing unit

Publications (2)

Publication Number Publication Date
JPS5638636A true JPS5638636A (en) 1981-04-13
JPS6218943B2 JPS6218943B2 (en) 1987-04-25

Family

ID=14631367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11418779A Granted JPS5638636A (en) 1979-09-07 1979-09-07 Data processing unit

Country Status (1)

Country Link
JP (1) JPS5638636A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01263854A (en) * 1988-04-15 1989-10-20 Nec Corp Deciding system for memory parity error
JPH02148343A (en) * 1988-11-30 1990-06-07 Nec Corp Memory parity error discriminating system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS554740A (en) * 1978-06-27 1980-01-14 Nec Corp Address monitor system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS554740A (en) * 1978-06-27 1980-01-14 Nec Corp Address monitor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01263854A (en) * 1988-04-15 1989-10-20 Nec Corp Deciding system for memory parity error
JPH02148343A (en) * 1988-11-30 1990-06-07 Nec Corp Memory parity error discriminating system

Also Published As

Publication number Publication date
JPS6218943B2 (en) 1987-04-25

Similar Documents

Publication Publication Date Title
JPS5797151A (en) Instruction storage device
JPS5539994A (en) Multiprocessor system
JPS5638636A (en) Data processing unit
JPS5570997A (en) Error bit check system for read only memory
JPS5694598A (en) Memory error correction control system
JPS5622291A (en) Bit error correction method for memory
JPS5637899A (en) Memory malfunction detection system
JPS56117400A (en) Buffer memory control system
JPS5617442A (en) Parity error processing system
JPS5680867A (en) Memory system
JPS57198599A (en) Memory device having redundancy
JPS5533276A (en) Read/write control system for memory unit
JPS57172582A (en) Cash memory control method
JPS5595152A (en) Microinstruction execution control system
JPS57100698A (en) Error correction system
JPS54129948A (en) Data processor
JPS5693191A (en) Memory error correction and automatic diagnosis system
JPS5696336A (en) Processing system for multilayer level microprogram
JPS55157043A (en) Information processor
JPS5798197A (en) Multiplexing memory device
JPS5727342A (en) Error checking system for error detecting correcting circuit
JPS5680899A (en) Error amending processing system of memory device
JPS5537634A (en) Integrated-circuit device
JPS5564696A (en) Error correction system for memory
JPS57100697A (en) Error correction system