JPS5682960A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS5682960A
JPS5682960A JP15948679A JP15948679A JPS5682960A JP S5682960 A JPS5682960 A JP S5682960A JP 15948679 A JP15948679 A JP 15948679A JP 15948679 A JP15948679 A JP 15948679A JP S5682960 A JPS5682960 A JP S5682960A
Authority
JP
Japan
Prior art keywords
memory
bus
data
external
transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15948679A
Other languages
Japanese (ja)
Other versions
JPH0542025B2 (en
Inventor
Tsuneo Kinoshita
Fumitaka Sato
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15948679A priority Critical patent/JPS5682960A/en
Publication of JPS5682960A publication Critical patent/JPS5682960A/en
Publication of JPH0542025B2 publication Critical patent/JPH0542025B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enable to decrease the number of external connection pins greatly by inputting microinstructions from a control memory part and transmitting and receiving main memory information and input-output information via the same bus.
CONSTITUTION: Arithmetic controller 101, made into one chip of a very high scale integrated semiconductor device, is controlled by external control memory part 102 stored with a microprogram. Then, common bus 103 is provided as a common communication path between controller 101 and an external device and output data of control part 102, memory addresses and memory data of the main memory and I/O data arrive in time-division mode. The number of external connection pins can, therefore, be decreased greatly by transmitting and receiving those signals via bus 103.
COPYRIGHT: (C)1981,JPO&Japio
JP15948679A 1979-12-08 1979-12-08 Bus control system Granted JPS5682960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15948679A JPS5682960A (en) 1979-12-08 1979-12-08 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15948679A JPS5682960A (en) 1979-12-08 1979-12-08 Bus control system

Publications (2)

Publication Number Publication Date
JPS5682960A true JPS5682960A (en) 1981-07-07
JPH0542025B2 JPH0542025B2 (en) 1993-06-25

Family

ID=15694815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15948679A Granted JPS5682960A (en) 1979-12-08 1979-12-08 Bus control system

Country Status (1)

Country Link
JP (1) JPS5682960A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513741A (en) * 1974-06-26 1976-01-13 Ibm
JPS52102643A (en) * 1976-02-25 1977-08-29 Hitachi Ltd Data processor
JPS5393741A (en) * 1977-01-26 1978-08-17 Hokushin Electric Works Duplex data transfer system
JPS5437438A (en) * 1977-08-27 1979-03-19 Nec Corp Bus control system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513741A (en) * 1974-06-26 1976-01-13 Ibm
JPS52102643A (en) * 1976-02-25 1977-08-29 Hitachi Ltd Data processor
JPS5393741A (en) * 1977-01-26 1978-08-17 Hokushin Electric Works Duplex data transfer system
JPS5437438A (en) * 1977-08-27 1979-03-19 Nec Corp Bus control system

Also Published As

Publication number Publication date
JPH0542025B2 (en) 1993-06-25

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