JPS5622124A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5622124A
JPS5622124A JP9759479A JP9759479A JPS5622124A JP S5622124 A JPS5622124 A JP S5622124A JP 9759479 A JP9759479 A JP 9759479A JP 9759479 A JP9759479 A JP 9759479A JP S5622124 A JPS5622124 A JP S5622124A
Authority
JP
Japan
Prior art keywords
transfer
rank
data
memory
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9759479A
Other languages
Japanese (ja)
Other versions
JPS6217780B2 (en
Inventor
Kazuhiko Uchiumi
Toshitaka Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9759479A priority Critical patent/JPS5622124A/en
Publication of JPS5622124A publication Critical patent/JPS5622124A/en
Publication of JPS6217780B2 publication Critical patent/JPS6217780B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To realize an automatic data transfer with the designated number and without processing the transfer data by the lower-rank CPU, by providing the address counter which is renewed by the DMA controller with every transfer of data at the lower-rank side.
CONSTITUTION: Address counter AC9 is provided at the side of lower-rank CPU4. The DMA transfer is carried out directly between memory 2 of the higher-rank CPU1 side and memory 5 of the lower-rank CPU4 side. In this case, DMA controller DMAC3 of the higher-rank side performs the control for the storing address of the transfer data of memory 2 and the number of transfers. And the storing address of the transfer data of memory 5 is controlled by AC9. The initial setting is given to AC9 at first by CPU4 and based on the program before starting the transfer of DMA. After this, AC9 is renewed successively by the strobe signal for data transfer delivered from DMAC3 with every transfer of the data by DMA and then sets the storing address of memory 5.
COPYRIGHT: (C)1981,JPO&Japio
JP9759479A 1979-07-31 1979-07-31 Data transfer system Granted JPS5622124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9759479A JPS5622124A (en) 1979-07-31 1979-07-31 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9759479A JPS5622124A (en) 1979-07-31 1979-07-31 Data transfer system

Publications (2)

Publication Number Publication Date
JPS5622124A true JPS5622124A (en) 1981-03-02
JPS6217780B2 JPS6217780B2 (en) 1987-04-20

Family

ID=14196554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9759479A Granted JPS5622124A (en) 1979-07-31 1979-07-31 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5622124A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5999522A (en) * 1982-11-30 1984-06-08 Canon Inc Input and output control system
JPS59141229U (en) * 1983-03-12 1984-09-20 株式会社クボタ Rotation synchronized transmission
JPS62217770A (en) * 1986-03-19 1987-09-25 Canon Inc Memory control circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363834A (en) * 1976-11-18 1978-06-07 Nippon Telegr & Teleph Corp <Ntt> End offering system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363834A (en) * 1976-11-18 1978-06-07 Nippon Telegr & Teleph Corp <Ntt> End offering system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5999522A (en) * 1982-11-30 1984-06-08 Canon Inc Input and output control system
JPS59141229U (en) * 1983-03-12 1984-09-20 株式会社クボタ Rotation synchronized transmission
JPS62217770A (en) * 1986-03-19 1987-09-25 Canon Inc Memory control circuit

Also Published As

Publication number Publication date
JPS6217780B2 (en) 1987-04-20

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