JPS5662343A - Electronic device - Google Patents

Electronic device

Info

Publication number
JPS5662343A
JPS5662343A JP13766779A JP13766779A JPS5662343A JP S5662343 A JPS5662343 A JP S5662343A JP 13766779 A JP13766779 A JP 13766779A JP 13766779 A JP13766779 A JP 13766779A JP S5662343 A JPS5662343 A JP S5662343A
Authority
JP
Japan
Prior art keywords
metal
layer
polyimide
carrier
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13766779A
Other languages
Japanese (ja)
Other versions
JPS6214943B2 (en
Inventor
Yasutoshi Kurihara
Mitsuo Taguchi
Koichi Inoue
Komei Yatsuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13766779A priority Critical patent/JPS5662343A/en
Publication of JPS5662343A publication Critical patent/JPS5662343A/en
Publication of JPS6214943B2 publication Critical patent/JPS6214943B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve the heat dissipating property through a metal layer comprising a copper layer and a metal solder layer in sold formation of a metal carrier for a semiconductor and a metal support therefor through a polyimide. CONSTITUTION:A metal carrier 15 for a semiconductor 11 and a metal support 12 therefor are formed solidly through a polyimide 13. Here, a metal layer comprising a copper layer 14 and a metal solder 14' are interposed between either the metal carrier 14 or the metal support 12 and the polyimide 13.
JP13766779A 1979-10-26 1979-10-26 Electronic device Granted JPS5662343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13766779A JPS5662343A (en) 1979-10-26 1979-10-26 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13766779A JPS5662343A (en) 1979-10-26 1979-10-26 Electronic device

Publications (2)

Publication Number Publication Date
JPS5662343A true JPS5662343A (en) 1981-05-28
JPS6214943B2 JPS6214943B2 (en) 1987-04-04

Family

ID=15203990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13766779A Granted JPS5662343A (en) 1979-10-26 1979-10-26 Electronic device

Country Status (1)

Country Link
JP (1) JPS5662343A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169912A (en) * 1982-03-31 1983-10-06 Hitachi Ltd Semiconductor device
JPS5952853A (en) * 1982-09-20 1984-03-27 Hitachi Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169912A (en) * 1982-03-31 1983-10-06 Hitachi Ltd Semiconductor device
JPS5952853A (en) * 1982-09-20 1984-03-27 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS6214943B2 (en) 1987-04-04

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