JPS5456766A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5456766A
JPS5456766A JP12365977A JP12365977A JPS5456766A JP S5456766 A JPS5456766 A JP S5456766A JP 12365977 A JP12365977 A JP 12365977A JP 12365977 A JP12365977 A JP 12365977A JP S5456766 A JPS5456766 A JP S5456766A
Authority
JP
Japan
Prior art keywords
solder
heat sink
plating
copper
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12365977A
Other languages
Japanese (ja)
Inventor
Hidetaka Ikuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12365977A priority Critical patent/JPS5456766A/en
Publication of JPS5456766A publication Critical patent/JPS5456766A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To obtain a semiconductor device which excels in the heat radiation effect by enhancing the mounting performance of the semiconductor element.
CONSTITUTION: Lead-tin group solder 3 is welded to copper heat sink 1 in the H2 atmosphere. The oxide on the surface of the copper and solder is removed to give Ni plating 2 of 3W10μm. When element 4 is mounted on the heat sink, plating film 2 enters solder layer 3 to eliminate the effect of the gas produced from the Ni plating. At the same time, the oxidation is avoided by the Ni film on the solder surface, so the solder and the element can be sticked together well. Thus, the oxide product is reduced with a uniform solder layer formed, ensuring an easy fixture between the element and the heat sink
COPYRIGHT: (C)1979,JPO&Japio
JP12365977A 1977-10-14 1977-10-14 Semiconductor device Pending JPS5456766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12365977A JPS5456766A (en) 1977-10-14 1977-10-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12365977A JPS5456766A (en) 1977-10-14 1977-10-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5456766A true JPS5456766A (en) 1979-05-08

Family

ID=14866088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12365977A Pending JPS5456766A (en) 1977-10-14 1977-10-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5456766A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846663A (en) * 1981-08-29 1983-03-18 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Rectifier with semiconductor diode thin piece
JPS63119242A (en) * 1986-11-07 1988-05-23 Toshiba Corp Circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846663A (en) * 1981-08-29 1983-03-18 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Rectifier with semiconductor diode thin piece
JPH0479140B2 (en) * 1981-08-29 1992-12-15 Bosch Gmbh Robert
JPS63119242A (en) * 1986-11-07 1988-05-23 Toshiba Corp Circuit board

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