JPS5656638A - Pattern forming method - Google Patents

Pattern forming method

Info

Publication number
JPS5656638A
JPS5656638A JP13389879A JP13389879A JPS5656638A JP S5656638 A JPS5656638 A JP S5656638A JP 13389879 A JP13389879 A JP 13389879A JP 13389879 A JP13389879 A JP 13389879A JP S5656638 A JPS5656638 A JP S5656638A
Authority
JP
Japan
Prior art keywords
sio2
etching
pattern
auxiliary
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13389879A
Other languages
Japanese (ja)
Inventor
Tadao Kato
Takaaki Katou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13389879A priority Critical patent/JPS5656638A/en
Publication of JPS5656638A publication Critical patent/JPS5656638A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain a metal layer of a desired pattern under high temperatures by a method wherein a main concavity of a given pattern is formed on a substrate itself with SiO2 working as a mask and an auxiliary concavity adjacently thereto through etching each, and after providing the metal layer in the concavities, the SiO2 mask is removed. CONSTITUTION:SiO2 12 and a resist 13 are laminated on a substrate 11, an electron beam 14 is irradiated thereto to obtain a given pattern formation 15 and auxiliary pattern formations 16 adjacently thereto. The main concavity 17 and the auxiliary concavities 18 are formed through etching, and a metal layer 19 of Nb is formed at temperature 200 deg.C or over. Next, from etching SiO2 12, both the main concavity and the auxiliary concavities are ready for etching therefrom, thus removing it quickly and easily. According to this constitution, undercut is not necessary for the resist 13 to form a pattern of mask layer, an excessive irradiation is not necessary at the time of patterning, a fine pattern can be formed, and SiO2 mask which involves a hardship for removal ever before can also be removed quickly.
JP13389879A 1979-10-13 1979-10-13 Pattern forming method Pending JPS5656638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13389879A JPS5656638A (en) 1979-10-13 1979-10-13 Pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13389879A JPS5656638A (en) 1979-10-13 1979-10-13 Pattern forming method

Publications (1)

Publication Number Publication Date
JPS5656638A true JPS5656638A (en) 1981-05-18

Family

ID=15115677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13389879A Pending JPS5656638A (en) 1979-10-13 1979-10-13 Pattern forming method

Country Status (1)

Country Link
JP (1) JPS5656638A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50132872A (en) * 1974-04-06 1975-10-21
JPS52127776A (en) * 1976-04-20 1977-10-26 Matsushita Electric Ind Co Ltd Semiconductor device and its preparation
JPS5333581A (en) * 1976-09-10 1978-03-29 Hitachi Ltd Production of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50132872A (en) * 1974-04-06 1975-10-21
JPS52127776A (en) * 1976-04-20 1977-10-26 Matsushita Electric Ind Co Ltd Semiconductor device and its preparation
JPS5333581A (en) * 1976-09-10 1978-03-29 Hitachi Ltd Production of semiconductor device

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