JPS5655060A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5655060A
JPS5655060A JP13103179A JP13103179A JPS5655060A JP S5655060 A JPS5655060 A JP S5655060A JP 13103179 A JP13103179 A JP 13103179A JP 13103179 A JP13103179 A JP 13103179A JP S5655060 A JPS5655060 A JP S5655060A
Authority
JP
Japan
Prior art keywords
isolating
groove
type
region
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13103179A
Other languages
Japanese (ja)
Inventor
Yoshito Ichinose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13103179A priority Critical patent/JPS5655060A/en
Publication of JPS5655060A publication Critical patent/JPS5655060A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain an element isolating structure with the lower layer portion of an epitaxial layer in a p-n junction isolating structure and with the upper layer portion in a V-shaped groove isolating structure, connecting both structures and thus reducing the area occupied by the element isolating band. CONSTITUTION:Boron is selectively diffused in p type semiconductor substrate 1, and a p type impurity region 12 is formed. When an n type epitaxial layer is grown on the surface, and a p type diffused region 6 is simultaneously formed. Subsequently, oxide silicon film 13 is formed on the surface, and a window is selectively opened at the same position as the p type impurity region 12. With the silicon film 13 as a mask it is etched with alkaline solution to form a groove 7 of V shape in cross section, and the bottom of the groove 7 is connected to the upper portion of the region 6. Since the width of the isolating groove can be reduced as compared with the conventional V-shaped groove isolating method, the integrity of the device can be improved.
JP13103179A 1979-10-11 1979-10-11 Semiconductor integrated circuit device Pending JPS5655060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13103179A JPS5655060A (en) 1979-10-11 1979-10-11 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13103179A JPS5655060A (en) 1979-10-11 1979-10-11 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5655060A true JPS5655060A (en) 1981-05-15

Family

ID=15048391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13103179A Pending JPS5655060A (en) 1979-10-11 1979-10-11 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5655060A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5879752A (en) * 1981-11-06 1983-05-13 Hitachi Ltd Semiconductor device
US5438221A (en) * 1990-01-24 1995-08-01 Harris Corporation Method and device in which bottoming of a well in a dielectrically isolated island is assured

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51132786A (en) * 1975-05-14 1976-11-18 Nec Corp Production method of semiconductor device
JPS51134081A (en) * 1975-05-16 1976-11-20 Fujitsu Ltd Method to manufacture semiconductor unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51132786A (en) * 1975-05-14 1976-11-18 Nec Corp Production method of semiconductor device
JPS51134081A (en) * 1975-05-16 1976-11-20 Fujitsu Ltd Method to manufacture semiconductor unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5879752A (en) * 1981-11-06 1983-05-13 Hitachi Ltd Semiconductor device
JPH0512863B2 (en) * 1981-11-06 1993-02-19 Hitachi Ltd
US5438221A (en) * 1990-01-24 1995-08-01 Harris Corporation Method and device in which bottoming of a well in a dielectrically isolated island is assured

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