JPS5649529A - Patterning method of doped layer - Google Patents
Patterning method of doped layerInfo
- Publication number
- JPS5649529A JPS5649529A JP12503479A JP12503479A JPS5649529A JP S5649529 A JPS5649529 A JP S5649529A JP 12503479 A JP12503479 A JP 12503479A JP 12503479 A JP12503479 A JP 12503479A JP S5649529 A JPS5649529 A JP S5649529A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- coated
- region
- substrate
- remained
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title abstract 2
- 238000000059 patterning Methods 0.000 title 1
- 239000010410 layer Substances 0.000 abstract 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 239000002184 metal Substances 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000011247 coating layer Substances 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
PURPOSE:To make it possible to form a fine pattern also against a thick metal layer by a method wherein in the case of a prescribed region of a substrate is selectively coated and a metal layer is doped wholly, the coated layer is removed with a metal layer thereupon, the metal layer is removed only on the substrate plane, a PSG layer is used as a coating layer. CONSTITUTION:An SiO2 layer 2 is coated on the semiconductor substrate 1, and a window is opened, a prescribed diffusion region 1' is formed within the substrate 1, the PSG layer 3 is generated on the whole phase by a CVD method while the SiO2 layer 2 is being remained. In the following, the mask of photo resist film 4 is provided on the layer 3 avoiding the region 1', the exposing portion of layer 3 is etching removed. At this time, the thickness of Al layer 5 to be formed at the later time is as thickness as approximately 1mum, the thickness of the layer 3 is made approximately 3mum, the overhang quantity of the remained layer 3 is made about 10mum. Thereafter, the Al layer 5 attached on the region 1' wholly is made isolate from the Al 5 coated on the layer 3, and the layer 3 is removed with the layer 5 thereupon and only the desired pattern Al layer 5 is remained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12503479A JPS5649529A (en) | 1979-09-28 | 1979-09-28 | Patterning method of doped layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12503479A JPS5649529A (en) | 1979-09-28 | 1979-09-28 | Patterning method of doped layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5649529A true JPS5649529A (en) | 1981-05-06 |
Family
ID=14900200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12503479A Pending JPS5649529A (en) | 1979-09-28 | 1979-09-28 | Patterning method of doped layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5649529A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52136588A (en) * | 1976-05-11 | 1977-11-15 | Fujitsu Ltd | Production of semiconductor device |
| JPS5338277A (en) * | 1976-09-21 | 1978-04-08 | Toshiba Corp | Production of semiconductor device |
-
1979
- 1979-09-28 JP JP12503479A patent/JPS5649529A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52136588A (en) * | 1976-05-11 | 1977-11-15 | Fujitsu Ltd | Production of semiconductor device |
| JPS5338277A (en) * | 1976-09-21 | 1978-04-08 | Toshiba Corp | Production of semiconductor device |
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