JPS5637665A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5637665A
JPS5637665A JP11380079A JP11380079A JPS5637665A JP S5637665 A JPS5637665 A JP S5637665A JP 11380079 A JP11380079 A JP 11380079A JP 11380079 A JP11380079 A JP 11380079A JP S5637665 A JPS5637665 A JP S5637665A
Authority
JP
Japan
Prior art keywords
region
type
layer
emitter
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11380079A
Other languages
Japanese (ja)
Inventor
Haruji Futami
Mamoru Fuse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11380079A priority Critical patent/JPS5637665A/en
Publication of JPS5637665A publication Critical patent/JPS5637665A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the current amplification factor of a semiconductor device and to improve the noise elimination characteristics thereof by reducing the thickness of an insulating film on the confronting portion between an emitter aned collector of a lateral transistor thinner than the other portion and extensively forming a low resistance substance becoming an emitter electrode thereon. CONSTITUTION:An N<+> type buried region region 4 is diffused in a P type Si substrate 1, an N type layer 2 becoming a base region including the region 4 is eptaxially grown, and the region 4 is simultaneously floated in the layer 2. An N<+> type base electrode pickup region 7 is further diffused then with P type collector region 6 in the same manner as a P type emitter region 5 in the surface layer of the layer 2, an insulating film 3 is coated on the entire surface, the film 3 disposed between the regions 5 and 6 is removed, and an insulating film 3' having a thickness of 500- 2300Angstrom is newly coated thereon. When a collector electrode 9 is formed on the region 6 or a base electrode 10 is formed on the region 7 thereafter, the emitter electrode 8 formed on the region 6 is creeped extensively on the thin film 3'.
JP11380079A 1979-09-05 1979-09-05 Semiconductor device Pending JPS5637665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11380079A JPS5637665A (en) 1979-09-05 1979-09-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11380079A JPS5637665A (en) 1979-09-05 1979-09-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5637665A true JPS5637665A (en) 1981-04-11

Family

ID=14621389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11380079A Pending JPS5637665A (en) 1979-09-05 1979-09-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5637665A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298040A (en) * 1988-10-04 1990-04-10 Toshiba Battery Co Ltd Manufacture of raw electrode sheet for spiral electrode
US6824925B2 (en) 2001-07-10 2004-11-30 Matsushita Electric Industrial Co., Ltd. Method for manufacturing base for electrode plate, method for manufacturing positive electrode plate and alkaline storage battery

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN=1976 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0298040A (en) * 1988-10-04 1990-04-10 Toshiba Battery Co Ltd Manufacture of raw electrode sheet for spiral electrode
US6824925B2 (en) 2001-07-10 2004-11-30 Matsushita Electric Industrial Co., Ltd. Method for manufacturing base for electrode plate, method for manufacturing positive electrode plate and alkaline storage battery

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