JPS5635472A - Mos type nonvolatile memory device - Google Patents

Mos type nonvolatile memory device

Info

Publication number
JPS5635472A
JPS5635472A JP11148579A JP11148579A JPS5635472A JP S5635472 A JPS5635472 A JP S5635472A JP 11148579 A JP11148579 A JP 11148579A JP 11148579 A JP11148579 A JP 11148579A JP S5635472 A JPS5635472 A JP S5635472A
Authority
JP
Japan
Prior art keywords
drain
voltage
writing
gate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11148579A
Other languages
Japanese (ja)
Inventor
Masanori Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11148579A priority Critical patent/JPS5635472A/en
Publication of JPS5635472A publication Critical patent/JPS5635472A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5614—Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain the nonvolatile memory having stable characteristics by forming a diffused layer having higher density than a substrate and the same type as the substrate partly in contact with the drain of a double gate MOSFET in a channel region and reducing the breakdown voltage between the diffused layer and the drain lower than the negative resistance generating voltage of the FET in a writing mode. CONSTITUTION:There are formed on the main surface of a P type Si 1 a field oxide film 3, a gate oxide film 4, a P-added polysilicon floating gate 5, a film 6 oxidized on the surface of the polysilicon 5, and a P-added polysilicon controlled gate 7. An N type source 8 and drain 9 are formed thereon, openings 10-12 are selectively perforated, and aluminum electrodes are provided therethrough. A P<+> type layer 16 is partly formed in the channel in contact with the drain 9, and the withstand junction voltage between the drain 9 and the layer 16 is set lower than the negative resistance generating voltage of the memory FET in case of writing operation mode. Even if the substrate and the source are grounded and sufficiently high voltage is applied to the controlled gate and the voltage of the same polarity is applied to the drain (in writing) no negative resistance occurs and discrete excessive writing phenomenon does not occur according to this configuration.
JP11148579A 1979-08-30 1979-08-30 Mos type nonvolatile memory device Pending JPS5635472A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11148579A JPS5635472A (en) 1979-08-30 1979-08-30 Mos type nonvolatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11148579A JPS5635472A (en) 1979-08-30 1979-08-30 Mos type nonvolatile memory device

Publications (1)

Publication Number Publication Date
JPS5635472A true JPS5635472A (en) 1981-04-08

Family

ID=14562451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11148579A Pending JPS5635472A (en) 1979-08-30 1979-08-30 Mos type nonvolatile memory device

Country Status (1)

Country Link
JP (1) JPS5635472A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0649172A2 (en) * 1993-10-15 1995-04-19 Sony Corporation Nonvolatile memory device and method of manufacturing same
US5586073A (en) * 1993-12-27 1996-12-17 Kabushiki Kaisha Toshiba Semiconductor device having a multi-layer channel structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0649172A2 (en) * 1993-10-15 1995-04-19 Sony Corporation Nonvolatile memory device and method of manufacturing same
US5814855A (en) * 1993-10-15 1998-09-29 Sony Corporation Nonvolatile memory device and method of manufacturing same
US5586073A (en) * 1993-12-27 1996-12-17 Kabushiki Kaisha Toshiba Semiconductor device having a multi-layer channel structure

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