JPS5621264A - Multiplex external memory unit - Google Patents

Multiplex external memory unit

Info

Publication number
JPS5621264A
JPS5621264A JP9692379A JP9692379A JPS5621264A JP S5621264 A JPS5621264 A JP S5621264A JP 9692379 A JP9692379 A JP 9692379A JP 9692379 A JP9692379 A JP 9692379A JP S5621264 A JPS5621264 A JP S5621264A
Authority
JP
Japan
Prior art keywords
memory unit
external memory
ctl4
register
status information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9692379A
Other languages
Japanese (ja)
Inventor
Norio Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Hokushin Electric Corp
Priority to JP9692379A priority Critical patent/JPS5621264A/en
Publication of JPS5621264A publication Critical patent/JPS5621264A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To increase the reliability of external memory unit with a simple constitution, by controlling the signal reception and giving and its operation between the bus and external memory unit and providing the main memory unit.
CONSTITUTION: The CTL4, 5 receive the instruction from CPU1 parallelly, starting is made to EMU6, 7 and the write-in operation is executed with the direct memory access. When CTL4, 5 detect the error state in the status information, the 3rd register is made by +1. When the CPU1 receives the error status information, the retrials are made by set number of times to check the content of the 3rd register of CTL4 and 5, and when it is more than the set number, it is disconnected from the line.
COPYRIGHT: (C)1981,JPO&Japio
JP9692379A 1979-07-30 1979-07-30 Multiplex external memory unit Pending JPS5621264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9692379A JPS5621264A (en) 1979-07-30 1979-07-30 Multiplex external memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9692379A JPS5621264A (en) 1979-07-30 1979-07-30 Multiplex external memory unit

Publications (1)

Publication Number Publication Date
JPS5621264A true JPS5621264A (en) 1981-02-27

Family

ID=14177867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9692379A Pending JPS5621264A (en) 1979-07-30 1979-07-30 Multiplex external memory unit

Country Status (1)

Country Link
JP (1) JPS5621264A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177061U (en) * 1987-04-24 1988-11-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177061U (en) * 1987-04-24 1988-11-16

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