JPS562030A - Input-output controller - Google Patents

Input-output controller

Info

Publication number
JPS562030A
JPS562030A JP7755879A JP7755879A JPS562030A JP S562030 A JPS562030 A JP S562030A JP 7755879 A JP7755879 A JP 7755879A JP 7755879 A JP7755879 A JP 7755879A JP S562030 A JPS562030 A JP S562030A
Authority
JP
Japan
Prior art keywords
control parts
circuits
slave
outputs
msw33
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7755879A
Other languages
Japanese (ja)
Inventor
Masakazu Kawamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7755879A priority Critical patent/JPS562030A/en
Publication of JPS562030A publication Critical patent/JPS562030A/en
Pending legal-status Critical Current

Links

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  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE: To improve the efficiency of utilization of a slave unit by automatizing the settlement of data access bus DAB, maintaining a load balance in the best state by automatizing the assignment of DAB by controlling matrix switch MSW.
CONSTITUTION: Two block multiplexer channel unit BMC1, 2 are connected to host interface IF circuits 31 and 23, the outputs of which are connected to respective columns of MSW33 of two rows by two columns. Two row outputs of MSW33 are connected to data passage control parts 34 and 35, MSW33 settles the data buses of control parts 34 and 35, and control parts 34 and 35 exercise data transfer control. The outputs of control parts 34 and 35 are led to column inputs of MSW36, whose row outputs are connected to slave units DXA 10, and DV13W20 via slave IF circuits 37 and 38 respectively. Respective IF circuits, MSWs, and data passage control parts are controlled by common control part 39 to select free DAB automatically and host and slave IF circuits are connected, so that the efficiency of utilization of the slave units will improve.
COPYRIGHT: (C)1981,JPO&Japio
JP7755879A 1979-06-21 1979-06-21 Input-output controller Pending JPS562030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7755879A JPS562030A (en) 1979-06-21 1979-06-21 Input-output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7755879A JPS562030A (en) 1979-06-21 1979-06-21 Input-output controller

Publications (1)

Publication Number Publication Date
JPS562030A true JPS562030A (en) 1981-01-10

Family

ID=13637336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7755879A Pending JPS562030A (en) 1979-06-21 1979-06-21 Input-output controller

Country Status (1)

Country Link
JP (1) JPS562030A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142647U (en) * 1985-08-01 1986-03-19 富士通株式会社 Cross call control device
JPH02214959A (en) * 1988-12-30 1990-08-27 Internatl Business Mach Corp <Ibm> Computer system and data processing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6142647U (en) * 1985-08-01 1986-03-19 富士通株式会社 Cross call control device
JPS6142187Y2 (en) * 1985-08-01 1986-12-01
JPH02214959A (en) * 1988-12-30 1990-08-27 Internatl Business Mach Corp <Ibm> Computer system and data processing method
JPH0583940B2 (en) * 1988-12-30 1993-11-30 Intaanashonaru Bijinesu Mashiinzu Corp

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