JPS5617060A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5617060A
JPS5617060A JP9254079A JP9254079A JPS5617060A JP S5617060 A JPS5617060 A JP S5617060A JP 9254079 A JP9254079 A JP 9254079A JP 9254079 A JP9254079 A JP 9254079A JP S5617060 A JPS5617060 A JP S5617060A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
wiring layer
region
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9254079A
Other languages
Japanese (ja)
Inventor
Tomio Nakano
Fumio Baba
Yoshihiro Takemae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9254079A priority Critical patent/JPS5617060A/en
Publication of JPS5617060A publication Critical patent/JPS5617060A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To easily program a semiconductor device due to burning off by flowing a current through a conductive layer crossed via an insulating layer for a wiring layer to preheat the wiring layer when selectively nonconducting the wiring region forming the semiconductor device. CONSTITUTION:A thick SiO2 film 7 is coated on an MOS active region formed in an Si substrate 2, the first wiring layer Fo is formed on a predetermined region thereon, the second wiring layer 10 is coated through an SiO2 film 11, and a fuse region F is formed with the wiring layers Fo and 10. Then, the layer 10 of the region F is burnt to be cut to program the semiconductor device. At this time 1/2- 1/3 of the programming current is flowed through the wiring layer Fo disposed under the layer 10 to enable burning to cut it with low current from an MOS transistor formed on the same substrate 2. In this manner, large current switching circuit becomes unnecessary to improve the integrity of the device as a whole.
JP9254079A 1979-07-23 1979-07-23 Semiconductor device Pending JPS5617060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9254079A JPS5617060A (en) 1979-07-23 1979-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9254079A JPS5617060A (en) 1979-07-23 1979-07-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5617060A true JPS5617060A (en) 1981-02-18

Family

ID=14057201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9254079A Pending JPS5617060A (en) 1979-07-23 1979-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5617060A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58167A (en) * 1981-06-25 1983-01-05 Fujitsu Ltd Semiconductor device
EP0078165A2 (en) * 1981-10-28 1983-05-04 Kabushiki Kaisha Toshiba A semiconductor device having a control wiring layer
JPS58123759A (en) * 1982-01-18 1983-07-23 Fujitsu Ltd Semiconductor memory storage
JPS5961061A (en) * 1982-09-30 1984-04-07 Fujitsu Ltd Manufacture of semiconductor device
JPS60261154A (en) * 1984-06-08 1985-12-24 Hitachi Micro Comput Eng Ltd Semiconductor device
EP0388341A2 (en) * 1989-03-14 1990-09-19 International Business Machines Corporation Method and apparatus for causing an open circuit in a conductive line

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58167A (en) * 1981-06-25 1983-01-05 Fujitsu Ltd Semiconductor device
JPH0332229B2 (en) * 1981-06-25 1991-05-10 Fujitsu Ltd
EP0078165A2 (en) * 1981-10-28 1983-05-04 Kabushiki Kaisha Toshiba A semiconductor device having a control wiring layer
US4814853A (en) * 1981-10-28 1989-03-21 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device with programmable fuse
JPS58123759A (en) * 1982-01-18 1983-07-23 Fujitsu Ltd Semiconductor memory storage
JPH0343788B2 (en) * 1982-01-18 1991-07-03 Fujitsu Ltd
JPS5961061A (en) * 1982-09-30 1984-04-07 Fujitsu Ltd Manufacture of semiconductor device
JPH0454985B2 (en) * 1982-09-30 1992-09-01 Fujitsu Ltd
JPS60261154A (en) * 1984-06-08 1985-12-24 Hitachi Micro Comput Eng Ltd Semiconductor device
JPH058579B2 (en) * 1984-06-08 1993-02-02 Hitachi Maikon Shisutemu Kk
EP0388341A2 (en) * 1989-03-14 1990-09-19 International Business Machines Corporation Method and apparatus for causing an open circuit in a conductive line

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