JPS56169435A - Phase synchronization oscillator - Google Patents
Phase synchronization oscillatorInfo
- Publication number
- JPS56169435A JPS56169435A JP7310080A JP7310080A JPS56169435A JP S56169435 A JPS56169435 A JP S56169435A JP 7310080 A JP7310080 A JP 7310080A JP 7310080 A JP7310080 A JP 7310080A JP S56169435 A JPS56169435 A JP S56169435A
- Authority
- JP
- Japan
- Prior art keywords
- phase
- output
- vco24
- vco21
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M7/00—Vibration-testing of structures; Shock-testing of structures
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To make the oscillating circuit of both systems to the same constitution completely, by enabling to produce two output signals in phase synchronism individually and at the some time through the use of two PLL ocillators. CONSTITUTION:An output signal of a voltage controlled oscillator VCO21 is fed back to a phase detector 22 and it is in phase comparison with the output signal of a VCO24. The output of the phase detector 22 is fed to the VCO21 via an LPF23 to control the oscillating frequency. On the other hand, the output of the VCO24 is fed back to a phase comparator 25 and it is compared for the phase with the output signal of the VCO21, and the output of the phase comparator 25 is converted into a DC signal via an LPF26 to control the frequency of the VCO24. Thus, if the characteristics of two PLL oscillators are equal, the oscillating frequency of the VCOs 21 and 24 is converged to (f1+DELTAf1/2) respectively and finally. Thus, independent signals having the frequencies of f1+DELTAf1 and f1 can be obtained from the terminals No.1 and No.2, respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7310080A JPS56169435A (en) | 1980-05-31 | 1980-05-31 | Phase synchronization oscillator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7310080A JPS56169435A (en) | 1980-05-31 | 1980-05-31 | Phase synchronization oscillator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56169435A true JPS56169435A (en) | 1981-12-26 |
Family
ID=13508563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7310080A Pending JPS56169435A (en) | 1980-05-31 | 1980-05-31 | Phase synchronization oscillator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56169435A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02134022A (en) * | 1988-11-15 | 1990-05-23 | Fujitsu Ltd | Dual system for clock generating circuit |
-
1980
- 1980-05-31 JP JP7310080A patent/JPS56169435A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02134022A (en) * | 1988-11-15 | 1990-05-23 | Fujitsu Ltd | Dual system for clock generating circuit |
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