JPS56159740A - Arithmetic controller - Google Patents

Arithmetic controller

Info

Publication number
JPS56159740A
JPS56159740A JP6363580A JP6363580A JPS56159740A JP S56159740 A JPS56159740 A JP S56159740A JP 6363580 A JP6363580 A JP 6363580A JP 6363580 A JP6363580 A JP 6363580A JP S56159740 A JPS56159740 A JP S56159740A
Authority
JP
Japan
Prior art keywords
instruction
bit
indirect branch
latch
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6363580A
Other languages
Japanese (ja)
Inventor
Hiroaki Yokomichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6363580A priority Critical patent/JPS56159740A/en
Publication of JPS56159740A publication Critical patent/JPS56159740A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30061—Multi-way branch instructions, e.g. CASE

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To begin a read at the starting address of an indirect branch instruction even if the number of address bit of firmware exceeds that of arithmetic bits of a bit-slicing logical operating circuit (ALU), by processing a fetch cycle and an execution cycle simultaneously. CONSTITUTION:For example, an instruction N holds the starting address of an indirect branch destination. As a clock C rises, the output of an instruction N-1 in a control memory 3 is held in a latch 4 and at the same time, the address of the instruction N appears in a program counter 2. High-order eight-bit outputs A and B in the latch 4 are analyzed by a decoder 5 to generate a drive signal for a driver 6. An output C obtained by the control memory 3 is inputted to an ALU1 via the driver 6 and at the same time, the instruction N is latched by the latch 4. The high- order eight-bit A and B of the instruction N are analyzed by the decoder 5. The low-order eight-bit outputs D and E and inputted to the ALU1 via a driver 7. Consequently, the starting address of the indirect branch destination is read in the ALU1 to execute the indirect branch instruction.
JP6363580A 1980-05-14 1980-05-14 Arithmetic controller Pending JPS56159740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6363580A JPS56159740A (en) 1980-05-14 1980-05-14 Arithmetic controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6363580A JPS56159740A (en) 1980-05-14 1980-05-14 Arithmetic controller

Publications (1)

Publication Number Publication Date
JPS56159740A true JPS56159740A (en) 1981-12-09

Family

ID=13234999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6363580A Pending JPS56159740A (en) 1980-05-14 1980-05-14 Arithmetic controller

Country Status (1)

Country Link
JP (1) JPS56159740A (en)

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