JPS56157560A - Operation control device - Google Patents
Operation control deviceInfo
- Publication number
- JPS56157560A JPS56157560A JP6104480A JP6104480A JPS56157560A JP S56157560 A JPS56157560 A JP S56157560A JP 6104480 A JP6104480 A JP 6104480A JP 6104480 A JP6104480 A JP 6104480A JP S56157560 A JPS56157560 A JP S56157560A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- supplied
- output signal
- microstep
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 abstract 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To shorten the processing time required for operations, by starting the next microstep to perform processings in parallel if the processing time of a microstep does not terminate within the basic time. CONSTITUTION:The output signal FENPR of an FF25 of a decimal operation module BPH12 is supplied to an NAND gate circuit 26 as a gate control command. The CBBSY signal to instruct extension of a microprogram is supplied to a circuit 26 also, and the output signal of the circuit 26 is supplied as the CMBSY signal to the K terminal of a J-KFF27 of a register and control module RCU10. When the CMBSY signal is 1 or 0, the FF27 makes the output signal FNDSY0 or 1-state by the rise of the CSCLK signal. This FNDSY signal is supplied to an inverter 28. The output signal of the inverter 28 is used as the CMDSY signal and as the starting signal for respective operating parts. Thus, even if the CBBSY signal becomes active, the next microstep is started.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6104480A JPS56157560A (en) | 1980-05-08 | 1980-05-08 | Operation control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6104480A JPS56157560A (en) | 1980-05-08 | 1980-05-08 | Operation control device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56157560A true JPS56157560A (en) | 1981-12-04 |
Family
ID=13159841
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6104480A Pending JPS56157560A (en) | 1980-05-08 | 1980-05-08 | Operation control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56157560A (en) |
-
1980
- 1980-05-08 JP JP6104480A patent/JPS56157560A/en active Pending
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