JPS5578322A - Input/output circuit of microcomputer - Google Patents

Input/output circuit of microcomputer

Info

Publication number
JPS5578322A
JPS5578322A JP15152978A JP15152978A JPS5578322A JP S5578322 A JPS5578322 A JP S5578322A JP 15152978 A JP15152978 A JP 15152978A JP 15152978 A JP15152978 A JP 15152978A JP S5578322 A JPS5578322 A JP S5578322A
Authority
JP
Japan
Prior art keywords
control signal
inversion
input
output
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15152978A
Other languages
Japanese (ja)
Inventor
Hidekazu Yabuuchi
Takashi Sakao
Kazuaki Mayumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15152978A priority Critical patent/JPS5578322A/en
Publication of JPS5578322A publication Critical patent/JPS5578322A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To cause a microcomputer itself to perform switching of positive logic and negative logic of I/O without addition of external circuits and data inversion dependent upon commands for every I/O.
CONSTITUTION: In case of positive logic, a circuit is the same state as connection between data bus 1 and latch input 15 and connection between external terminal 3 and driver input 17 by inactivating inversion control signal generation part 4 by inversion control signal 14. At an output command execution time, contents of data bus 1 are sent to latch input 15 through inversion circuit 9 as they are, and latch control signal 13 is activated by command decoder part 5 to output them as latch output 16, and simultaneously, command decoder part 5 activates driver control signal 11 to send them to external terminal 3 through driver 7, and as the result, the output processing of positive logic is performed. In case of negative logic, inversion control signal generation part 4 activates inversion control signal 14.
COPYRIGHT: (C)1980,JPO&Japio
JP15152978A 1978-12-06 1978-12-06 Input/output circuit of microcomputer Pending JPS5578322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15152978A JPS5578322A (en) 1978-12-06 1978-12-06 Input/output circuit of microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15152978A JPS5578322A (en) 1978-12-06 1978-12-06 Input/output circuit of microcomputer

Publications (1)

Publication Number Publication Date
JPS5578322A true JPS5578322A (en) 1980-06-12

Family

ID=15520498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15152978A Pending JPS5578322A (en) 1978-12-06 1978-12-06 Input/output circuit of microcomputer

Country Status (1)

Country Link
JP (1) JPS5578322A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015373A (en) * 1983-07-05 1985-01-26 三菱電機株式会社 Controller for elevator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015373A (en) * 1983-07-05 1985-01-26 三菱電機株式会社 Controller for elevator

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