JPS56148799A - Memory data processing system - Google Patents
Memory data processing systemInfo
- Publication number
- JPS56148799A JPS56148799A JP5249680A JP5249680A JPS56148799A JP S56148799 A JPS56148799 A JP S56148799A JP 5249680 A JP5249680 A JP 5249680A JP 5249680 A JP5249680 A JP 5249680A JP S56148799 A JPS56148799 A JP S56148799A
- Authority
- JP
- Japan
- Prior art keywords
- storage
- flag
- address
- data
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE:To attain easy and accurate restart access after interruption due to a power failure, etc., by writing a flag at an address position of a memory read successively. CONSTITUTION:In response to a request from an external device, CPU constituting a data processor together with storage 1 shifts the contents of storage 1 successively. In this shifting operation, data in address (i+1) of storage 1 is readout and written in data register 2. Next, a flag from flag register 3 is written in address (i+1) of storage 1. Further, the data written in register 2 is transferred to address (i) of storage 1 and a similar shift cycle is repeated. Therefore, when a power failure, etc., occur during shift cycle processing to interrupt the processing and the processing is restarted after its recovery, restart access is attained easily and accurately by referring to the flag.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5249680A JPS56148799A (en) | 1980-04-18 | 1980-04-18 | Memory data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5249680A JPS56148799A (en) | 1980-04-18 | 1980-04-18 | Memory data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56148799A true JPS56148799A (en) | 1981-11-18 |
Family
ID=12916321
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5249680A Pending JPS56148799A (en) | 1980-04-18 | 1980-04-18 | Memory data processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56148799A (en) |
-
1980
- 1980-04-18 JP JP5249680A patent/JPS56148799A/en active Pending
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