JPS56134746A - Method of forming wiring - Google Patents

Method of forming wiring

Info

Publication number
JPS56134746A
JPS56134746A JP3834280A JP3834280A JPS56134746A JP S56134746 A JPS56134746 A JP S56134746A JP 3834280 A JP3834280 A JP 3834280A JP 3834280 A JP3834280 A JP 3834280A JP S56134746 A JPS56134746 A JP S56134746A
Authority
JP
Japan
Prior art keywords
wiring
revivability
layer
ions
injected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3834280A
Other languages
Japanese (ja)
Inventor
Masaki Okayama
Tokuro Soma
Norihiro Kusumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3834280A priority Critical patent/JPS56134746A/en
Publication of JPS56134746A publication Critical patent/JPS56134746A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To easily and in good revivability obtain a wiring-pattern having a moderate inclination on a side surface of the end edge thereof by a method wherein ions are injected on an Al layer surface. CONSTITUTION:The Al layer 13 is formed on an insulating layer 2 on an Si substrate and injected with Ar ions. A resist mask 10 having the wiring pattern is formed to be etched and to form a wiring 14. At this time, an etching speed is high on the surface side due to the damage give by the ion-injection, so that the side etching is remarkably developed to enable the inclined plane 14a to be obtained on the edge side face. The resist mask 10 is removed to finish. A tilt angle can be formed arbitrarily accurately and in good revivability by selecting an ion-injection energy and a dosage.
JP3834280A 1980-03-26 1980-03-26 Method of forming wiring Pending JPS56134746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3834280A JPS56134746A (en) 1980-03-26 1980-03-26 Method of forming wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3834280A JPS56134746A (en) 1980-03-26 1980-03-26 Method of forming wiring

Publications (1)

Publication Number Publication Date
JPS56134746A true JPS56134746A (en) 1981-10-21

Family

ID=12522605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3834280A Pending JPS56134746A (en) 1980-03-26 1980-03-26 Method of forming wiring

Country Status (1)

Country Link
JP (1) JPS56134746A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5926815U (en) * 1982-08-12 1984-02-20 日立コンデンサ株式会社 conductive film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5926815U (en) * 1982-08-12 1984-02-20 日立コンデンサ株式会社 conductive film

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