JPS56130973A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56130973A
JPS56130973A JP3371280A JP3371280A JPS56130973A JP S56130973 A JPS56130973 A JP S56130973A JP 3371280 A JP3371280 A JP 3371280A JP 3371280 A JP3371280 A JP 3371280A JP S56130973 A JPS56130973 A JP S56130973A
Authority
JP
Japan
Prior art keywords
film
oxide film
drain region
gate oxide
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3371280A
Other languages
Japanese (ja)
Inventor
Kunihiko Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3371280A priority Critical patent/JPS56130973A/en
Publication of JPS56130973A publication Critical patent/JPS56130973A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the effect of a hot carrier when a short channel effect preventing remedy is employed by forming a thick gate oxide film end corresponding to the channel side end of a drain region, thereby shortening the channel of an MIS field effect transistor. CONSTITUTION:A field oxide film 6 and a gate oxide film 7 are formed on a P type silicon semiconductor substrate 1, and a polycrystalline silicon film 8 and a silicon nitride film 9 are further formed thereon. The part 7a corresponding to the channel side end of the drain region of a gate oxide film 7 is formed thickly. Subsequently, a silicon gate electrode 8G is formed, and the film 7 is patterned. Then, an n<+> type source region 10S and an n<+> type drain region 10D are formed by ion injection. Thereafter, a phosphosilicate glass film 11, a source electrode 12S, a gate electrode 12G and a drain electrode 12D are formed thereon.
JP3371280A 1980-03-17 1980-03-17 Manufacture of semiconductor device Pending JPS56130973A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3371280A JPS56130973A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3371280A JPS56130973A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56130973A true JPS56130973A (en) 1981-10-14

Family

ID=12394018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3371280A Pending JPS56130973A (en) 1980-03-17 1980-03-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56130973A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2676864A1 (en) * 1991-05-23 1992-11-27 Samsung Electronics Co Ltd Method of fabricating an MOS transistor with gate-drain overlap and corresponding structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52147983A (en) * 1976-06-03 1977-12-08 Nec Corp Insulation gate type semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52147983A (en) * 1976-06-03 1977-12-08 Nec Corp Insulation gate type semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2676864A1 (en) * 1991-05-23 1992-11-27 Samsung Electronics Co Ltd Method of fabricating an MOS transistor with gate-drain overlap and corresponding structure

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