JPS56114185A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS56114185A
JPS56114185A JP1738380A JP1738380A JPS56114185A JP S56114185 A JPS56114185 A JP S56114185A JP 1738380 A JP1738380 A JP 1738380A JP 1738380 A JP1738380 A JP 1738380A JP S56114185 A JPS56114185 A JP S56114185A
Authority
JP
Japan
Prior art keywords
readout
write
counter
memory
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1738380A
Other languages
Japanese (ja)
Inventor
Shigeki Okamoto
Haruhiko Tsunoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1738380A priority Critical patent/JPS56114185A/en
Publication of JPS56114185A publication Critical patent/JPS56114185A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To decrease overhead of a memory, by identifying the difference of a readout memory module from a waite-in one at swap operation, making write-in operation after the readout if they are same, and overlapping the readout and write- in if they are different. CONSTITUTION:In swap operation where readout and write-in are continuously made, if the readout and write-in memory modules are the same, the start signal CMGO from CPU is fed to the memory to start the readout. At the same time, the busy signal is ON and the time required for readout is set to the counter. When the value of counter is zero, readout is finished. The time required for write-in is also set in the counter to start write-in, and when the counter is zero, the swap operation is finished. If the modules are different from each other, the set value to the counter is controlled with the counter control signal to overlap readout and write-in.
JP1738380A 1980-02-14 1980-02-14 Memory access control system Pending JPS56114185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1738380A JPS56114185A (en) 1980-02-14 1980-02-14 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1738380A JPS56114185A (en) 1980-02-14 1980-02-14 Memory access control system

Publications (1)

Publication Number Publication Date
JPS56114185A true JPS56114185A (en) 1981-09-08

Family

ID=11942478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1738380A Pending JPS56114185A (en) 1980-02-14 1980-02-14 Memory access control system

Country Status (1)

Country Link
JP (1) JPS56114185A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04148441A (en) * 1990-10-12 1992-05-21 Fujitsu Ltd Stage control system for data processing system
US7159067B2 (en) 1999-02-18 2007-01-02 Hitachi, Ltd. Information processing apparatus using index and TAG addresses for cache

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04148441A (en) * 1990-10-12 1992-05-21 Fujitsu Ltd Stage control system for data processing system
US7159067B2 (en) 1999-02-18 2007-01-02 Hitachi, Ltd. Information processing apparatus using index and TAG addresses for cache

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