JPS5651087A - Refresh control system - Google Patents
Refresh control systemInfo
- Publication number
- JPS5651087A JPS5651087A JP12706279A JP12706279A JPS5651087A JP S5651087 A JPS5651087 A JP S5651087A JP 12706279 A JP12706279 A JP 12706279A JP 12706279 A JP12706279 A JP 12706279A JP S5651087 A JPS5651087 A JP S5651087A
- Authority
- JP
- Japan
- Prior art keywords
- memory cycle
- refresh
- cycle operation
- refresh control
- control system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To enable to refresh RAMs surely with a simple circuit constitution, by giving priority to the refresh operation according to the refresh request signal than the memory cycle operation. CONSTITUTION:When a refresh request signal is fed to a RAM system, a WAIT signal is fed to a CPU1 from a system 2. Thus, the memory cycle operation in the CPU1 is extended to gieven priority over the RAM of the system 2 than the memory cycle operation. Accordingly, the refresh control of RAMs can be ensured with a simple circuit constitution such as the stop of clock of memory cycle operation and whether or not in memory cycle.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12706279A JPS5651087A (en) | 1979-10-02 | 1979-10-02 | Refresh control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12706279A JPS5651087A (en) | 1979-10-02 | 1979-10-02 | Refresh control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5651087A true JPS5651087A (en) | 1981-05-08 |
Family
ID=14950639
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12706279A Pending JPS5651087A (en) | 1979-10-02 | 1979-10-02 | Refresh control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5651087A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61115607U (en) * | 1984-12-28 | 1986-07-22 | ||
JPH0253292A (en) * | 1988-08-17 | 1990-02-22 | Sharp Corp | Dynamic memory |
US4969055A (en) * | 1984-10-10 | 1990-11-06 | Oberjatzas Guenter | Method for recording and/or reproducing digitally coded signals with interframe and interframe coding |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4991136A (en) * | 1972-12-29 | 1974-08-30 | ||
JPS5391637A (en) * | 1977-01-24 | 1978-08-11 | Nec Corp | Data processor |
-
1979
- 1979-10-02 JP JP12706279A patent/JPS5651087A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4991136A (en) * | 1972-12-29 | 1974-08-30 | ||
JPS5391637A (en) * | 1977-01-24 | 1978-08-11 | Nec Corp | Data processor |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4969055A (en) * | 1984-10-10 | 1990-11-06 | Oberjatzas Guenter | Method for recording and/or reproducing digitally coded signals with interframe and interframe coding |
JPS61115607U (en) * | 1984-12-28 | 1986-07-22 | ||
JPH0253292A (en) * | 1988-08-17 | 1990-02-22 | Sharp Corp | Dynamic memory |
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