JPS5721146A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS5721146A
JPS5721146A JP9607380A JP9607380A JPS5721146A JP S5721146 A JPS5721146 A JP S5721146A JP 9607380 A JP9607380 A JP 9607380A JP 9607380 A JP9607380 A JP 9607380A JP S5721146 A JPS5721146 A JP S5721146A
Authority
JP
Japan
Prior art keywords
transmission
data
timing
circuit
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9607380A
Other languages
Japanese (ja)
Inventor
Toshimitsu Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9607380A priority Critical patent/JPS5721146A/en
Publication of JPS5721146A publication Critical patent/JPS5721146A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To smoothly perform data transmission and reception between devices in different processing speeds, by providing a timing memory which can output the corresponding timing value in response to the transmission data. CONSTITUTION:Data and timing information between data corresponding to the data are set to a timing memory write-in control register 8 before the transmission of data via a data bus from a central controller. Next, data 11' is written in a timing memory 3 with the instruction of a write-in control signal 11''. A transmission circuit 2 transmits the transmission data sequentially when a transmission data 12' and a control information 12'' are inputted. A timing circuit 4 is started from a control signal 13' of a timing circuit 4 formed with the readout data 13'' and the transmission data 12'' from the transmission data 12' and the control information 12''. When the transmission circuit 2 completes the transmission of all the transmission data, it gives a transmission completion signal 7 to an AND circuit 6. On the other hand, the AND circuit 6 is stopped with a signal 5 until the timing value of the timing memory 3 is at ''0'', and the report possible for transmission is not made to the transmission side.
JP9607380A 1980-07-14 1980-07-14 Data transmission system Pending JPS5721146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9607380A JPS5721146A (en) 1980-07-14 1980-07-14 Data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9607380A JPS5721146A (en) 1980-07-14 1980-07-14 Data transmission system

Publications (1)

Publication Number Publication Date
JPS5721146A true JPS5721146A (en) 1982-02-03

Family

ID=14155224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9607380A Pending JPS5721146A (en) 1980-07-14 1980-07-14 Data transmission system

Country Status (1)

Country Link
JP (1) JPS5721146A (en)

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