JPS5596644A - Method of bonding semiconductor device - Google Patents
Method of bonding semiconductor deviceInfo
- Publication number
- JPS5596644A JPS5596644A JP362679A JP362679A JPS5596644A JP S5596644 A JPS5596644 A JP S5596644A JP 362679 A JP362679 A JP 362679A JP 362679 A JP362679 A JP 362679A JP S5596644 A JPS5596644 A JP S5596644A
- Authority
- JP
- Japan
- Prior art keywords
- tool
- semiconductor device
- pawls
- arrow
- designated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE: To execute a bonding work by entirely eliminating the respective positioning works for respective lead frames regardless of the perforating pitch error and film elongation.
CONSTITUTION: Pawls 19 are initially located at the position 22, lowered to insert into an aperture 13', and moved as designated by an arrow b to the position 20 for positioning. Then, the pawls 19 are raised as designated by an arrow c from the aperture 13' to be thus returned to the position 22 as designated by an arrow d to thus wait for next lead frame feed signal. In this state the bonding tool 8, the lead frame 15, and the semiconductor device can be confirmed for positioning. When they are displaced, the pawls 19 or the tool 8 is aligned and fixed. Then, the tool 8 is lowered to bond the lead wire to the electrode terminal. The semiconductor device is separated from the adhered substrate, and the tool 8 is simultaneously raised to the original position. Then the next semiconductor device is supplied under the tool 8 in high accuracy. Thus, the lead wire can be accurately positioned at its feeding position.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP362679A JPS5596644A (en) | 1979-01-16 | 1979-01-16 | Method of bonding semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP362679A JPS5596644A (en) | 1979-01-16 | 1979-01-16 | Method of bonding semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5596644A true JPS5596644A (en) | 1980-07-23 |
Family
ID=11562698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP362679A Pending JPS5596644A (en) | 1979-01-16 | 1979-01-16 | Method of bonding semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5596644A (en) |
-
1979
- 1979-01-16 JP JP362679A patent/JPS5596644A/en active Pending
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