JPS5588149A - Output unit for semiconductor integrated circuit - Google Patents

Output unit for semiconductor integrated circuit

Info

Publication number
JPS5588149A
JPS5588149A JP16275178A JP16275178A JPS5588149A JP S5588149 A JPS5588149 A JP S5588149A JP 16275178 A JP16275178 A JP 16275178A JP 16275178 A JP16275178 A JP 16275178A JP S5588149 A JPS5588149 A JP S5588149A
Authority
JP
Japan
Prior art keywords
logic
circuit
transferred
integrated circuit
output unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16275178A
Other languages
Japanese (ja)
Inventor
Masaki Ogawa
Akira Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16275178A priority Critical patent/JPS5588149A/en
Publication of JPS5588149A publication Critical patent/JPS5588149A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To make a test by generating logic level [1] or [0] in a needed state and at a needed point in time from a buffer circuit driving an external connection circuit connected to LSI according to a control signal obtained by a control circuit.
CONSTITUTION: When testing clocks are inputted to controller 11, output circuits A and B generate logic [0] or [1]. When logic [0] or [1] is transferred to output circuit B, control signal D transferred from logic circuit 10 can control tri-state 14 to high impedance or low impedance. When logic [0] or [1] is transferred to output circuit A, information signal C transferred from logic circuit 1 makes it possible to obtain logic [0] or [1] from exclusive-OR circuit 12-1 corresponding to the input.
COPYRIGHT: (C)1980,JPO&Japio
JP16275178A 1978-12-27 1978-12-27 Output unit for semiconductor integrated circuit Pending JPS5588149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16275178A JPS5588149A (en) 1978-12-27 1978-12-27 Output unit for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16275178A JPS5588149A (en) 1978-12-27 1978-12-27 Output unit for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5588149A true JPS5588149A (en) 1980-07-03

Family

ID=15760556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16275178A Pending JPS5588149A (en) 1978-12-27 1978-12-27 Output unit for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5588149A (en)

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