JPS5578339A - Multiplication system - Google Patents

Multiplication system

Info

Publication number
JPS5578339A
JPS5578339A JP15252878A JP15252878A JPS5578339A JP S5578339 A JPS5578339 A JP S5578339A JP 15252878 A JP15252878 A JP 15252878A JP 15252878 A JP15252878 A JP 15252878A JP S5578339 A JPS5578339 A JP S5578339A
Authority
JP
Japan
Prior art keywords
digit
inputted
multiple table
operand
additions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15252878A
Other languages
Japanese (ja)
Inventor
Norimitsu Kagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP15252878A priority Critical patent/JPS5578339A/en
Publication of JPS5578339A publication Critical patent/JPS5578339A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the number of additions in operation of each digit to improve the processing speed of operation by generating a multiple table, which is obtained by multiplying an operated number by 1...9, previously and reading data from the multiple table according to operands and adding them.
CONSTITUTION: Memory 19 stores multiple data obtained by multiplying an operated number by 1...9, and a digit is designated by line address LAT, and write is desiganted by write command WT. Data read from memory 19 is inputted to B register 12. Then, an operand is inputted to D register 14, and the output is inputted to four-bit buffer 20, and input signals are read synchronously with control signal YM. In this system, the number of additions can be reduced in calculation of each digit to improve the processing speed of operation by reading data from the multiple table according to the operand and adding them.
COPYRIGHT: (C)1980,JPO&Japio
JP15252878A 1978-12-09 1978-12-09 Multiplication system Pending JPS5578339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15252878A JPS5578339A (en) 1978-12-09 1978-12-09 Multiplication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15252878A JPS5578339A (en) 1978-12-09 1978-12-09 Multiplication system

Publications (1)

Publication Number Publication Date
JPS5578339A true JPS5578339A (en) 1980-06-12

Family

ID=15542399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15252878A Pending JPS5578339A (en) 1978-12-09 1978-12-09 Multiplication system

Country Status (1)

Country Link
JP (1) JPS5578339A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029865A (en) * 1983-07-29 1985-02-15 Hitachi Ltd Logical simulation system by history registration
JPS60163128A (en) * 1984-02-02 1985-08-26 Nec Corp Multiplier circuit
JPS60254372A (en) * 1984-05-31 1985-12-16 Nippon Precision Saakitsutsu Kk Arithmetic unit for sum of products

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6029865A (en) * 1983-07-29 1985-02-15 Hitachi Ltd Logical simulation system by history registration
JPH0472269B2 (en) * 1983-07-29 1992-11-17 Hitachi Ltd
JPS60163128A (en) * 1984-02-02 1985-08-26 Nec Corp Multiplier circuit
JPH0447849B2 (en) * 1984-02-02 1992-08-05 Nippon Electric Co
JPS60254372A (en) * 1984-05-31 1985-12-16 Nippon Precision Saakitsutsu Kk Arithmetic unit for sum of products

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