JPS555526A - Automatic level set unit of digital type - Google Patents
Automatic level set unit of digital typeInfo
- Publication number
- JPS555526A JPS555526A JP7814178A JP7814178A JPS555526A JP S555526 A JPS555526 A JP S555526A JP 7814178 A JP7814178 A JP 7814178A JP 7814178 A JP7814178 A JP 7814178A JP S555526 A JPS555526 A JP S555526A
- Authority
- JP
- Japan
- Prior art keywords
- input signal
- value
- switch
- level
- outputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000000994 depressogenic effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/001—Digital control of analog signals
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To set the input signal to optimum level, by holding the input signal level after A/D conversion and controlling the attenuation of the resistor attenuators located on the transmission line digitally. CONSTITUTION:When the switch 8 si depressed, the input signal is converted 9 to the DC voltage corresponding to the peak level, and the sample value of a given period is A/D converted 7. The clock pulse is generated 10, it is fed to the digital counter 5 via the AND gates 12,13, and the count value corresponding to the sample value is outputted. The maximum value of the count value is held with the latch circuit 14 and the comparator 15, the maximum values B1 to B4 are outputted for the switch depression period, the analog switches 18,22,26,30 of the resistor attenuator group 3 are controlled to control the overall attenuation. When the switch 8 is turned off, the counter 5 does not count and clear, and the latch circuit keeps the value before. Thus, automatic setting at the optimum level can be made without compressing the dynamic range of input signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53078141A JPS6017172B2 (en) | 1978-06-27 | 1978-06-27 | Digital automatic level setting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53078141A JPS6017172B2 (en) | 1978-06-27 | 1978-06-27 | Digital automatic level setting device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS555526A true JPS555526A (en) | 1980-01-16 |
JPS6017172B2 JPS6017172B2 (en) | 1985-05-01 |
Family
ID=13653594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53078141A Expired JPS6017172B2 (en) | 1978-06-27 | 1978-06-27 | Digital automatic level setting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6017172B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5629146A (en) * | 1979-08-20 | 1981-03-23 | Toshiba Corp | Photometric sensor of immersion type |
JPS57113541U (en) * | 1980-12-29 | 1982-07-14 | ||
JPS57152740A (en) * | 1981-03-17 | 1982-09-21 | Hitachi Cable Ltd | Optical receiving circuit |
JPS5813006A (en) * | 1981-07-16 | 1983-01-25 | Matsushita Electric Ind Co Ltd | Automatic level controller |
JPS58220510A (en) * | 1982-06-16 | 1983-12-22 | Tokyo Keiki Co Ltd | Temperature compensating circuit of encoder |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62190201U (en) * | 1986-05-24 | 1987-12-03 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53116253U (en) * | 1977-02-24 | 1978-09-16 |
-
1978
- 1978-06-27 JP JP53078141A patent/JPS6017172B2/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53116253U (en) * | 1977-02-24 | 1978-09-16 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5629146A (en) * | 1979-08-20 | 1981-03-23 | Toshiba Corp | Photometric sensor of immersion type |
JPS57113541U (en) * | 1980-12-29 | 1982-07-14 | ||
JPS57152740A (en) * | 1981-03-17 | 1982-09-21 | Hitachi Cable Ltd | Optical receiving circuit |
JPS5813006A (en) * | 1981-07-16 | 1983-01-25 | Matsushita Electric Ind Co Ltd | Automatic level controller |
JPH0330322B2 (en) * | 1981-07-16 | 1991-04-30 | ||
JPS58220510A (en) * | 1982-06-16 | 1983-12-22 | Tokyo Keiki Co Ltd | Temperature compensating circuit of encoder |
Also Published As
Publication number | Publication date |
---|---|
JPS6017172B2 (en) | 1985-05-01 |
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