JPS5539487A - Receiving device - Google Patents

Receiving device

Info

Publication number
JPS5539487A
JPS5539487A JP14806578A JP14806578A JPS5539487A JP S5539487 A JPS5539487 A JP S5539487A JP 14806578 A JP14806578 A JP 14806578A JP 14806578 A JP14806578 A JP 14806578A JP S5539487 A JPS5539487 A JP S5539487A
Authority
JP
Japan
Prior art keywords
contents
counter
divider
channel selection
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14806578A
Other languages
Japanese (ja)
Other versions
JPS5652498B2 (en
Inventor
Osamu Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14806578A priority Critical patent/JPS5539487A/en
Publication of JPS5539487A publication Critical patent/JPS5539487A/en
Publication of JPS5652498B2 publication Critical patent/JPS5652498B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE: To ensure the reception over a wide range of frequency by varying the division ratio of the divider to change the contents of the channel selection counter, memorizing previously the contents of the channel selection counter of the receivable broadcast station and then reading and displaying the contents of the memory.
CONSTITUTION: Channel selection counter 14 is provided to count the output of the channel selection pulse generator, along with 1/N divider 9 whose division ratio is controlled by the output of counter 14 plus frequency comparator 10 which gives a comparison to the output phase between reference oscillator 11 and divider 9. Thus the PLL circuit is formed to control the frequency of the local osicllator of front end 1 by the output of comparator 10. Then the contents of counter 14 is changed by the control of control part CTL, and then varying division ratio N of divider 9 to detect the receivable broadcast station. The contents of counter 14 corresponding to the receivable broadcast station is memorized in memories 59N and 59P via binary-decimal decoder 20, and then the contents of these memories are read out through part CTL to be displayed to plane display device 47.
COPYRIGHT: (C)1980,JPO&Japio
JP14806578A 1978-11-29 1978-11-29 Receiving device Granted JPS5539487A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14806578A JPS5539487A (en) 1978-11-29 1978-11-29 Receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14806578A JPS5539487A (en) 1978-11-29 1978-11-29 Receiving device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9605671A Division JPS555729B2 (en) 1971-11-29 1971-11-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP17153180A Division JPS56107626A (en) 1980-12-05 1980-12-05 Synthesizer receiver

Publications (2)

Publication Number Publication Date
JPS5539487A true JPS5539487A (en) 1980-03-19
JPS5652498B2 JPS5652498B2 (en) 1981-12-12

Family

ID=15444403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14806578A Granted JPS5539487A (en) 1978-11-29 1978-11-29 Receiving device

Country Status (1)

Country Link
JP (1) JPS5539487A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5762020U (en) * 1980-09-30 1982-04-13
JPS5772416A (en) * 1980-10-07 1982-05-06 Furuno Electric Co Ltd Controller for receiving frequency of receiver
JPH01142222U (en) * 1988-03-18 1989-09-29

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5129368A (en) * 1974-09-05 1976-03-12 Daikin Ind Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5129368A (en) * 1974-09-05 1976-03-12 Daikin Ind Ltd

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5762020U (en) * 1980-09-30 1982-04-13
JPS5772416A (en) * 1980-10-07 1982-05-06 Furuno Electric Co Ltd Controller for receiving frequency of receiver
JPH01142222U (en) * 1988-03-18 1989-09-29

Also Published As

Publication number Publication date
JPS5652498B2 (en) 1981-12-12

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