JPS5533228A

JPS5533228A - Arithmetic unit

Info

Publication number: JPS5533228A
Application number: JP10578178A
Authority: JP
Inventors: Tomohiro Shimizu
Original assignee: Casio Computer Co Ltd
Current assignee: Casio Computer Co Ltd
Priority date: 1978-08-30
Filing date: 1978-08-30
Publication date: 1980-03-08

Abstract

PURPOSE: To increase a processing time by equalizing the minimum machine cycle of an arithmetic unit using RAM to two-bit time by setting the read-out timing of a 2nd buffer to the leading edge of a writing pulse to RAM.

CONSTITUTION: Row addresses S and F from a microprogram controller assign operated and operational registers in RAM 20 at timing t₁ and at timing t₂ respectively and column addresses also assign sequentially digits of both the registers at timing t₁ through controller 23. Once a column address for an arithmetic start is given, the assigned-digit content of the operated register is read out to buffer 25 in building-up time of clock ϕ₁ of timing t₁ and in builing-up time of clock ϕ₁ of next timing t₂, the assigned-digit content of the operational register is read out to buffer 26. In the output period of timing signal t₂.ϕ₁, both contents of gates 27 and 28 are added together via adder 29 and written to the operational register.