JPS5533225A - Arithmetic unit - Google Patents

Arithmetic unit

Info

Publication number
JPS5533225A
JPS5533225A JP10577878A JP10577878A JPS5533225A JP S5533225 A JPS5533225 A JP S5533225A JP 10577878 A JP10577878 A JP 10577878A JP 10577878 A JP10577878 A JP 10577878A JP S5533225 A JPS5533225 A JP S5533225A
Authority
JP
Japan
Prior art keywords
clock pulse
time
ram
assigned
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10577878A
Other languages
Japanese (ja)
Inventor
Tomohiro Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP10577878A priority Critical patent/JPS5533225A/en
Publication of JPS5533225A publication Critical patent/JPS5533225A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To equalize a minimum machine cycle to one-bit time by using RAM in two-part structure which is read in downward time of a clock pulse and written in time from the fall of the clock pulse until its rise.
CONSTITUTION: From a microprogram controller, row addresses of 1st and 2nd RAMs 21 and 22 are outputted and by them, operated register A in the 2nd RAM and operational register B in the 1st RAM are assigned. Column addresses, on the other hand, are outputted to address counter 23 whose contents advance by clock pulse ϕ2 and address controller 24, so that digits of registers A and B will be assigned. In the downward time of 1st clock pulse ϕ1, the contents of the lowest digits of registers B and A are read out at the same time to 1st and 2nd buffers 27 and 28 and while clock pulse ϕ1 is in a fall state, addition is performed and its result is written to register A. At the same time, next column addresses are assigned.
COPYRIGHT: (C)1980,JPO&Japio
JP10577878A 1978-08-30 1978-08-30 Arithmetic unit Pending JPS5533225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10577878A JPS5533225A (en) 1978-08-30 1978-08-30 Arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10577878A JPS5533225A (en) 1978-08-30 1978-08-30 Arithmetic unit

Publications (1)

Publication Number Publication Date
JPS5533225A true JPS5533225A (en) 1980-03-08

Family

ID=14416604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10577878A Pending JPS5533225A (en) 1978-08-30 1978-08-30 Arithmetic unit

Country Status (1)

Country Link
JP (1) JPS5533225A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911017A (en) * 1972-05-26 1974-01-31
JPS5295940A (en) * 1976-02-09 1977-08-12 Hitachi Ltd Computer processing control

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911017A (en) * 1972-05-26 1974-01-31
JPS5295940A (en) * 1976-02-09 1977-08-12 Hitachi Ltd Computer processing control

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