JPS5513930A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device

Info

Publication number
JPS5513930A
JPS5513930A JP8672778A JP8672778A JPS5513930A JP S5513930 A JPS5513930 A JP S5513930A JP 8672778 A JP8672778 A JP 8672778A JP 8672778 A JP8672778 A JP 8672778A JP S5513930 A JPS5513930 A JP S5513930A
Authority
JP
Japan
Prior art keywords
deposited
defect
nature
crystal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8672778A
Other languages
Japanese (ja)
Inventor
Kunihiro Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8672778A priority Critical patent/JPS5513930A/en
Publication of JPS5513930A publication Critical patent/JPS5513930A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To prevent weakness in characteristics by injecting a life time killer into the defective portions provided selectably and previously in the portion not associated with the characteristics to be deposited.
CONSTITUTION: an impurity useful for a life time killer such as Au, Pt and others has in general the nature being deposited in the portion having the crystal or the defect on the Si substrate. By making use of this nature, when the crystal or the defect has been formed by a chemical etching process or an ion implantation in the location at which the characteristics of the semiconductor chip may not be suffered from an undesirable influence, for example a dicing line, pad portion, or a field portion, the crystalization is caused at those locations. When a Pt layer attached to the back face of the substrate is heated in the closed tube under the N2 atmosphere at 900°C, 30 minutes, Pt would be deposited in the dicing portion.
COPYRIGHT: (C)1980,JPO&Japio
JP8672778A 1978-07-18 1978-07-18 Manufacturing method for semiconductor device Pending JPS5513930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8672778A JPS5513930A (en) 1978-07-18 1978-07-18 Manufacturing method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8672778A JPS5513930A (en) 1978-07-18 1978-07-18 Manufacturing method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5513930A true JPS5513930A (en) 1980-01-31

Family

ID=13894881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8672778A Pending JPS5513930A (en) 1978-07-18 1978-07-18 Manufacturing method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5513930A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848964A (en) * 1981-09-18 1983-03-23 Toyo Electric Mfg Co Ltd Forming method for junction of reverse conducting thyristor
JPS5852873A (en) * 1981-09-25 1983-03-29 Toyo Electric Mfg Co Ltd Forming method for junction of reverse conducting thyristor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848964A (en) * 1981-09-18 1983-03-23 Toyo Electric Mfg Co Ltd Forming method for junction of reverse conducting thyristor
JPS5852873A (en) * 1981-09-25 1983-03-29 Toyo Electric Mfg Co Ltd Forming method for junction of reverse conducting thyristor

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