JPS55133552A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS55133552A JPS55133552A JP4012679A JP4012679A JPS55133552A JP S55133552 A JPS55133552 A JP S55133552A JP 4012679 A JP4012679 A JP 4012679A JP 4012679 A JP4012679 A JP 4012679A JP S55133552 A JPS55133552 A JP S55133552A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- integrated circuit
- layer
- island region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To provide a universal integrated circuit simply in high integrity by forming an island region of the same conducting type as a high impurity density buried layer directly over a high impurity density buried region in a semiconductor substrate, making the island region contact with the buried layer and thus forming a transistor, resistors and the like on the island region. CONSTITUTION:An n<+>type buried layer 2 is selectively formed on the surface of a p-type semiconductor substrate 1. A p-type epitaxial layer 3 is then formed thereon, and an n-type region 4 is formed by an ion implantation process. Unit functions of npn transistor, diode, resistors and the like are then formed in the n-type ion implanted region 4. A resistor 9 and a MOS transistor 10 as also formed on the region where n-type ion is not implanted of the layer 3. An isolation is conducted by thick oxide films 5. Thus, the epitaxial layer of the same conducting type as the substrate is formed to form an island region therein by a simple electric isolation to reduce the margin in designing it so as to enhance the integrity of the semiconductor integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4012679A JPS55133552A (en) | 1979-04-03 | 1979-04-03 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4012679A JPS55133552A (en) | 1979-04-03 | 1979-04-03 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55133552A true JPS55133552A (en) | 1980-10-17 |
Family
ID=12572116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4012679A Pending JPS55133552A (en) | 1979-04-03 | 1979-04-03 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55133552A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5011680A (en) * | 1973-06-01 | 1975-02-06 |
-
1979
- 1979-04-03 JP JP4012679A patent/JPS55133552A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5011680A (en) * | 1973-06-01 | 1975-02-06 |
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