JPS5512736A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method

Info

Publication number
JPS5512736A
JPS5512736A JP8536278A JP8536278A JPS5512736A JP S5512736 A JPS5512736 A JP S5512736A JP 8536278 A JP8536278 A JP 8536278A JP 8536278 A JP8536278 A JP 8536278A JP S5512736 A JPS5512736 A JP S5512736A
Authority
JP
Japan
Prior art keywords
silver
main body
gold
heat
soldering member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8536278A
Other languages
Japanese (ja)
Inventor
Yoichi Ushiyama
Makoto Tomita
Naomi Suyama
Yoshihiko Azuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP8536278A priority Critical patent/JPS5512736A/en
Publication of JPS5512736A publication Critical patent/JPS5512736A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To enable a semiconductor to be better adhered to a heat radiating plate and improve its heat dissipating performance by forming a bold or a silver film of 0.7W2.0μ in thickness on a soldering member surface so as to protect it from being oxidized.
CONSTITUTION: A tape-like soldering member 3, forming a 0.7W2.0μ thick gold or silver covering layer 2 which is activating the surface of a gold-tin system or a silver-tin system solder main body 1, is cut to a required length. Now, thus cut soldering member 3a is placed on the top of a heat-radiating plate 4. If the heat- radiating palte 4 is heated up to melting point of the soldering material 3 or to a higher temperature, the solder main body 1 starts being melted. And, at the same time, gold or silver constituting the covering layer 2 is dispersed onto the solder main body 1, and a soldering member 3 consisting of gold or silver and the solder main body 1 is formed in a molten state. The semiconductor element 5 is sucked and held by a collet having an indentation on its bottom surface, and it is placed onto the member 3a.
COPYRIGHT: (C)1980,JPO&Japio
JP8536278A 1978-07-13 1978-07-13 Semiconductor device manufacturing method Pending JPS5512736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8536278A JPS5512736A (en) 1978-07-13 1978-07-13 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8536278A JPS5512736A (en) 1978-07-13 1978-07-13 Semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
JPS5512736A true JPS5512736A (en) 1980-01-29

Family

ID=13856593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8536278A Pending JPS5512736A (en) 1978-07-13 1978-07-13 Semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JPS5512736A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851584A (en) * 1981-09-24 1983-03-26 Hitachi Ltd Mounting structure of compound semiconductor element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851584A (en) * 1981-09-24 1983-03-26 Hitachi Ltd Mounting structure of compound semiconductor element

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