JPS5761338A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS5761338A
JPS5761338A JP13622480A JP13622480A JPS5761338A JP S5761338 A JPS5761338 A JP S5761338A JP 13622480 A JP13622480 A JP 13622480A JP 13622480 A JP13622480 A JP 13622480A JP S5761338 A JPS5761338 A JP S5761338A
Authority
JP
Japan
Prior art keywords
circuit
counter
output
period
alternating pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13622480A
Other languages
Japanese (ja)
Other versions
JPS6340369B2 (en
Inventor
Masashi Hirome
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13622480A priority Critical patent/JPS5761338A/en
Publication of JPS5761338A publication Critical patent/JPS5761338A/en
Publication of JPS6340369B2 publication Critical patent/JPS6340369B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54—Ring counters, i.e. feedback shift register counters

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To make a frequency division circuit unnecessary, by obtaining the alternating pulse having period of two times of set value of a counter circuit by utilizing the flip-flop of the retaining on the higher rank of a counter circuit. CONSTITUTION:In case of periodical hexamerous system counter, flip-flop of the 4th stage of the higher rank of the 4 bits binary counter 1 is retained. Logical output of ''AND NOT'' circuit 2 becomes 0 when the counter value of this circuit is 5, and by the next clock, this hexamerous counter is set in initial condition. Output condition of an output terminal Q3 is read from an input terminal P3 with the inversed condition by the ''NOT'' circuit 3 by performing this clock. Output of the terminal Q3 is inversed. Hereinafter these operations are repeatedly executed. Then, alternating pulse having the period of 12 clocks is obtained at the output terminal Q3, i.e. alternating pulse having the period of two times of the set value in the counter circuit can be obtained.
JP13622480A 1980-09-30 1980-09-30 Counter circuit Granted JPS5761338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13622480A JPS5761338A (en) 1980-09-30 1980-09-30 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13622480A JPS5761338A (en) 1980-09-30 1980-09-30 Counter circuit

Publications (2)

Publication Number Publication Date
JPS5761338A true JPS5761338A (en) 1982-04-13
JPS6340369B2 JPS6340369B2 (en) 1988-08-10

Family

ID=15170190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13622480A Granted JPS5761338A (en) 1980-09-30 1980-09-30 Counter circuit

Country Status (1)

Country Link
JP (1) JPS5761338A (en)

Also Published As

Publication number Publication date
JPS6340369B2 (en) 1988-08-10

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