JPS6482559A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6482559A JPS6482559A JP24019987A JP24019987A JPS6482559A JP S6482559 A JPS6482559 A JP S6482559A JP 24019987 A JP24019987 A JP 24019987A JP 24019987 A JP24019987 A JP 24019987A JP S6482559 A JPS6482559 A JP S6482559A
- Authority
- JP
- Japan
- Prior art keywords
- high melting
- melting metal
- etching
- contact holes
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To avoid etching of silicon substrate at the time of forming contact holes, and prevent punch through of junction, by forming a high melting metal layer having an area larger than the sectional view of the contact hole on an impurity diffusion region formed on a semiconductor substrate. CONSTITUTION:After diffusion regions 2, 3, a gate oxide film 5 and a gate electrode 6 are formed, high melting metal like titanium is deposited, and patternized to form high melting metal layers 7, 8. Next an interlayer insulating film 9 of, e.g., PSG is deposited, and, on the high melting metal layer, 7, 8, are formed contact holes 12, 13 whose sectional views are smaller than the layers 7, 8. Then wirings 10, 11 of, e.g, aluminum are formed. In an etching process to make the contact holes in the interlayer insulating film 9, since the high melting metal layers 7, 8 exist, the etching does not reach a silicon substrate, even if over etching is performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24019987A JPS6482559A (en) | 1987-09-24 | 1987-09-24 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24019987A JPS6482559A (en) | 1987-09-24 | 1987-09-24 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6482559A true JPS6482559A (en) | 1989-03-28 |
Family
ID=17055932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24019987A Pending JPS6482559A (en) | 1987-09-24 | 1987-09-24 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6482559A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02105536A (en) * | 1988-10-14 | 1990-04-18 | Seiko Epson Corp | Semiconductor device |
| US5327003A (en) * | 1991-03-08 | 1994-07-05 | Fujitsu Limited | Semiconductor static RAM having thin film transistor gate connection |
| US5391894A (en) * | 1991-03-01 | 1995-02-21 | Fujitsu Limited | Static random access memory device having thin film transistor loads |
-
1987
- 1987-09-24 JP JP24019987A patent/JPS6482559A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02105536A (en) * | 1988-10-14 | 1990-04-18 | Seiko Epson Corp | Semiconductor device |
| US5391894A (en) * | 1991-03-01 | 1995-02-21 | Fujitsu Limited | Static random access memory device having thin film transistor loads |
| US5516715A (en) * | 1991-03-01 | 1996-05-14 | Fujitsu Limited | Method of producing static random access memory device having thin film transister loads |
| US5327003A (en) * | 1991-03-08 | 1994-07-05 | Fujitsu Limited | Semiconductor static RAM having thin film transistor gate connection |
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