JPS5475954A - Data channel unit - Google Patents

Data channel unit

Info

Publication number
JPS5475954A
JPS5475954A JP14273477A JP14273477A JPS5475954A JP S5475954 A JPS5475954 A JP S5475954A JP 14273477 A JP14273477 A JP 14273477A JP 14273477 A JP14273477 A JP 14273477A JP S5475954 A JPS5475954 A JP S5475954A
Authority
JP
Japan
Prior art keywords
control section
μprg
input
unit
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14273477A
Other languages
Japanese (ja)
Inventor
Mitsuhiro Yamaga
Akinori Kagotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14273477A priority Critical patent/JPS5475954A/en
Publication of JPS5475954A publication Critical patent/JPS5475954A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain the unit small and low in cost, by providing the microprogram controller independently of the channel controller CHC controlling a plurality of channel units CH, and the channel unit CH controlling the input and output units.
CONSTITUTION: CHC1 memorizes the microprogram μPRG, and consists of the μPRG control section 3 executing with sequential readout, CPU interface control section 4, main memory unit MEM interface control section 3, CH interface control section 6 and the control section 7 for the buffer memory and CHC internal part, and it executes the data transfer operation between MEM and the input and output unit according to the input and output instruction from CPU. CH2 is constituted with the μPRG control section 8, CHC interface register group 9,I/O interface latch group 10, and CH internal control register group 11, controlling a plurality of input and output controller. Accordingly, μPRG can respond to required functions, then small size and economical unit can be made.
COPYRIGHT: (C)1979,JPO&Japio
JP14273477A 1977-11-30 1977-11-30 Data channel unit Pending JPS5475954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14273477A JPS5475954A (en) 1977-11-30 1977-11-30 Data channel unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14273477A JPS5475954A (en) 1977-11-30 1977-11-30 Data channel unit

Publications (1)

Publication Number Publication Date
JPS5475954A true JPS5475954A (en) 1979-06-18

Family

ID=15322328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14273477A Pending JPS5475954A (en) 1977-11-30 1977-11-30 Data channel unit

Country Status (1)

Country Link
JP (1) JPS5475954A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114054A (en) * 1978-02-27 1979-09-05 Toshiba Corp Channel control system
JPS54114137A (en) * 1978-02-27 1979-09-06 Toshiba Corp Channel control system
JPS54114138A (en) * 1978-02-27 1979-09-06 Toshiba Corp Channel control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54114054A (en) * 1978-02-27 1979-09-05 Toshiba Corp Channel control system
JPS54114137A (en) * 1978-02-27 1979-09-06 Toshiba Corp Channel control system
JPS54114138A (en) * 1978-02-27 1979-09-06 Toshiba Corp Channel control system

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