JPS55119741A - Operation circuit - Google Patents

Operation circuit

Info

Publication number
JPS55119741A
JPS55119741A JP2612079A JP2612079A JPS55119741A JP S55119741 A JPS55119741 A JP S55119741A JP 2612079 A JP2612079 A JP 2612079A JP 2612079 A JP2612079 A JP 2612079A JP S55119741 A JPS55119741 A JP S55119741A
Authority
JP
Japan
Prior art keywords
input
processor
registers
output
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2612079A
Other languages
Japanese (ja)
Other versions
JPS616407B2 (en
Inventor
Itaru Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2612079A priority Critical patent/JPS55119741A/en
Publication of JPS55119741A publication Critical patent/JPS55119741A/en
Publication of JPS616407B2 publication Critical patent/JPS616407B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the execution time of instruction word and to enable effective operation, by selectively contacting either one of input or output of the microprocessor to the input of the external register input.
CONSTITUTION: The microprocessor 11 has the internal register group 31 in the internal part, the external registers 12 and 14 are provided external the processor 11, and the input is connected to the input of the processor. Further, the selection unit 21 is provided between the output of the processor 11 and the input of the registers 12 and 14. Either one of the output or input of the processor 11 is selectively connected to the input of the registers 12 and 14. Thus, the idle time of the processor 11 is made short and the number of steps of microprogram, the execution time of instruction word is reduced to enable effective operation.
COPYRIGHT: (C)1980,JPO&Japio
JP2612079A 1979-03-08 1979-03-08 Operation circuit Granted JPS55119741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2612079A JPS55119741A (en) 1979-03-08 1979-03-08 Operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2612079A JPS55119741A (en) 1979-03-08 1979-03-08 Operation circuit

Publications (2)

Publication Number Publication Date
JPS55119741A true JPS55119741A (en) 1980-09-13
JPS616407B2 JPS616407B2 (en) 1986-02-26

Family

ID=12184705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2612079A Granted JPS55119741A (en) 1979-03-08 1979-03-08 Operation circuit

Country Status (1)

Country Link
JP (1) JPS55119741A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03157722A (en) * 1989-11-15 1991-07-05 Matsushita Electric Ind Co Ltd Floating point arithmetic unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03157722A (en) * 1989-11-15 1991-07-05 Matsushita Electric Ind Co Ltd Floating point arithmetic unit

Also Published As

Publication number Publication date
JPS616407B2 (en) 1986-02-26

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