JPS5475940A - Memory control system - Google Patents
Memory control systemInfo
- Publication number
- JPS5475940A JPS5475940A JP14276077A JP14276077A JPS5475940A JP S5475940 A JPS5475940 A JP S5475940A JP 14276077 A JP14276077 A JP 14276077A JP 14276077 A JP14276077 A JP 14276077A JP S5475940 A JPS5475940 A JP S5475940A
- Authority
- JP
- Japan
- Prior art keywords
- defective
- counter
- memory
- information
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0875—Organisation of a plurality of magnetic shift registers
Landscapes
- Shift Register Type Memory (AREA)
Abstract
PURPOSE:To realize the memory control system easy for constitution, by providing the memory storing the accumulated information for the defective group with the memory group storing the information of non-defective and defective loop group in a plurality of information loops of shift register memories. CONSTITUTION:Corresponding to the additional memories 20 and 21 writhing in ''0'' to the address N if the Nth loop group is good and ''1'' if defective, the memories 160 and 161 which write in the difference between the Nth normal loop group number Nm and N to the address N and store the information of the accumulating number of the defective loop group are provided. At a certain time, the address register 4 is collated with the time counter 3, and even if the transfer display FF7 is turned on, the content of the memory 160 is read out at the accumulating display counter 170, and if it is more than 1, the output of the gate 140 and the defective display signal 13 are 1, and no data transfer is made. When time is advanced and the counter 170 is counter down into 0, the output of the gate 180 is 0, and the output of FF7 is inputted from the gate 8 to the transfer control circuit 9, starting transfer.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14276077A JPS5475940A (en) | 1977-11-30 | 1977-11-30 | Memory control system |
DE2817134A DE2817134C2 (en) | 1977-04-20 | 1978-04-19 | Storage control system |
US05/897,692 US4233669A (en) | 1977-04-20 | 1978-04-19 | Redundant bubble memory control system |
SE7804449A SE434686B (en) | 1977-04-20 | 1978-04-19 | Memory controller |
GB15720/78A GB1595410A (en) | 1977-04-20 | 1978-04-20 | Memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14276077A JPS5475940A (en) | 1977-11-30 | 1977-11-30 | Memory control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5475940A true JPS5475940A (en) | 1979-06-18 |
JPS5721787B2 JPS5721787B2 (en) | 1982-05-10 |
Family
ID=15322931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14276077A Granted JPS5475940A (en) | 1977-04-20 | 1977-11-30 | Memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5475940A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6285475B2 (en) | 2016-01-29 | 2018-02-28 | ファナック株式会社 | Motor drive device having discharge function |
-
1977
- 1977-11-30 JP JP14276077A patent/JPS5475940A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5721787B2 (en) | 1982-05-10 |
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