JPS5443714A - Signal recording and reproducing apparatus - Google Patents

Signal recording and reproducing apparatus

Info

Publication number
JPS5443714A
JPS5443714A JP11067977A JP11067977A JPS5443714A JP S5443714 A JPS5443714 A JP S5443714A JP 11067977 A JP11067977 A JP 11067977A JP 11067977 A JP11067977 A JP 11067977A JP S5443714 A JPS5443714 A JP S5443714A
Authority
JP
Japan
Prior art keywords
bits
polarity
frame synchronous
channel
synchronous signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11067977A
Other languages
Japanese (ja)
Inventor
Teruo Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11067977A priority Critical patent/JPS5443714A/en
Publication of JPS5443714A publication Critical patent/JPS5443714A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To make it possible to easily produce demodulation clock by recording the portions having more 0 bits in a reversed manner and by supplying frame synchronous signals with code patterns corresponding to the information indicating the recording polarity.
CONSTITUTION: When the date in a channel have more 1 bits, they are allowed to pass as they are, whereas when they have more 0 bits they are made to pass with a reversed polarity. As a result, 1 bits become more at all times. The information indicating the polarity of the data coding operation of the channel for reproduction is fed to a frame synchronous signal producing circuit 7. The data thus coded are fed to the circuit 7. The frame synchronous signals are generated and added to the both channel data from polarity control circuits 6r and 6l. At this time, the frame synchronous signals are formed into bit pattern.
COPYRIGHT: (C)1979,JPO&Japio
JP11067977A 1977-09-13 1977-09-13 Signal recording and reproducing apparatus Pending JPS5443714A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11067977A JPS5443714A (en) 1977-09-13 1977-09-13 Signal recording and reproducing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11067977A JPS5443714A (en) 1977-09-13 1977-09-13 Signal recording and reproducing apparatus

Publications (1)

Publication Number Publication Date
JPS5443714A true JPS5443714A (en) 1979-04-06

Family

ID=14541697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11067977A Pending JPS5443714A (en) 1977-09-13 1977-09-13 Signal recording and reproducing apparatus

Country Status (1)

Country Link
JP (1) JPS5443714A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5144876A (en) * 1989-06-02 1992-09-08 Yamaha Corporation Electronic musical instrument capable of performing a tone control responsive to an after-touch operation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5144876A (en) * 1989-06-02 1992-09-08 Yamaha Corporation Electronic musical instrument capable of performing a tone control responsive to an after-touch operation

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