GB2011229A - Encoding and decoding of digital data - Google Patents
Encoding and decoding of digital dataInfo
- Publication number
- GB2011229A GB2011229A GB7843161A GB7843161A GB2011229A GB 2011229 A GB2011229 A GB 2011229A GB 7843161 A GB7843161 A GB 7843161A GB 7843161 A GB7843161 A GB 7843161A GB 2011229 A GB2011229 A GB 2011229A
- Authority
- GB
- United Kingdom
- Prior art keywords
- code
- cell
- decoding
- data
- transition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
A binary code (B) or NRZ code (C), is encoded into a code (M) to obtain the highest packing density of information for recording the data on a recording medium. Decoding of code (M) into an NRZ code is also disclosed. The code (M) includes signal level transitions, both at the middle and at the start of data cell intervals. The code (M) avoids any space between successive signal level transitions greater than two data signal intervals such as are possible in the NRZ code. Binary 1 is represented by a midcell transition in either sense, or as a cell boundary transition, spaced by one cell from the last transition. Any transitions separated by two bit cells are known to occur on the cell boundaries, and can be used for synchronisation recovery. <IMAGE>
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US84855077A | 1977-11-04 | 1977-11-04 | |
AU82947/82A AU530226B2 (en) | 1977-11-04 | 1982-04-22 | Digital decoder |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2011229A true GB2011229A (en) | 1979-07-04 |
GB2011229B GB2011229B (en) | 1982-08-11 |
Family
ID=25640103
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB7843161A Expired GB2011229B (en) | 1977-11-04 | 1978-11-03 | Encoding and decoding of digital data |
Country Status (9)
Country | Link |
---|---|
JP (1) | JPS5474715A (en) |
AU (2) | AU523034B2 (en) |
BE (1) | BE871748A (en) |
CA (1) | CA1136279A (en) |
CH (1) | CH647366A5 (en) |
DE (1) | DE2847833C2 (en) |
FR (1) | FR2408247A1 (en) |
GB (1) | GB2011229B (en) |
NL (1) | NL7810901A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2209908A (en) * | 1987-09-15 | 1989-05-24 | Plessey Co Plc | A bi-phase modulator |
GB2287622A (en) * | 1994-03-17 | 1995-09-20 | Nissan Motor | Multiplex serial data communication circuit network for a motor control system |
WO2024000811A1 (en) * | 2022-06-29 | 2024-01-04 | 长鑫存储技术有限公司 | Clock control circuit and semiconductor memory |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2571910B1 (en) * | 1984-10-16 | 1987-01-09 | Bull Sa | ENCODING AND DECODING METHOD AND DEVICE FOR SERIAL TRANSMISSION OF BINARY DATA WITH CONTINUOUS COMPONENT REMOVAL |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1323299A (en) * | 1970-03-16 | 1973-07-11 | British Aircraft Corp Ltd | Data recording methods and apparatus |
US3750121A (en) * | 1971-06-18 | 1973-07-31 | Honeywell Inc | Address marker encoder in three frequency recording |
US3815122A (en) * | 1973-01-02 | 1974-06-04 | Gte Information Syst Inc | Data converting apparatus |
FR2234708B1 (en) * | 1973-06-22 | 1976-09-17 | Thomson Csf | |
US3988729A (en) * | 1975-01-29 | 1976-10-26 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Differential pulse code modulation |
US4027335A (en) * | 1976-03-19 | 1977-05-31 | Ampex Corporation | DC free encoding for data transmission system |
-
1978
- 1978-10-27 AU AU41144/78A patent/AU523034B2/en not_active Expired
- 1978-10-31 CA CA000315347A patent/CA1136279A/en not_active Expired
- 1978-10-31 CH CH1120678A patent/CH647366A5/en not_active IP Right Cessation
- 1978-11-02 JP JP13467578A patent/JPS5474715A/en active Pending
- 1978-11-02 NL NL7810901A patent/NL7810901A/en not_active Application Discontinuation
- 1978-11-03 FR FR7831204A patent/FR2408247A1/en active Granted
- 1978-11-03 BE BE191521A patent/BE871748A/en not_active IP Right Cessation
- 1978-11-03 GB GB7843161A patent/GB2011229B/en not_active Expired
- 1978-11-03 DE DE19782847833 patent/DE2847833C2/en not_active Expired
-
1982
- 1982-04-22 AU AU82947/82A patent/AU530226B2/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2209908A (en) * | 1987-09-15 | 1989-05-24 | Plessey Co Plc | A bi-phase modulator |
GB2287622A (en) * | 1994-03-17 | 1995-09-20 | Nissan Motor | Multiplex serial data communication circuit network for a motor control system |
US5600634A (en) * | 1994-03-17 | 1997-02-04 | Nissan Motor Co., Ltd. | Multiplex serial data communication circuit network with superposed clock and data signals |
GB2287622B (en) * | 1994-03-17 | 1998-10-28 | Nissan Motor | Multiplex serial data communication circuit network and method and motor control system and method using multiplex serial data communication circuit network |
WO2024000811A1 (en) * | 2022-06-29 | 2024-01-04 | 长鑫存储技术有限公司 | Clock control circuit and semiconductor memory |
Also Published As
Publication number | Publication date |
---|---|
AU530226B2 (en) | 1983-07-07 |
CA1136279A (en) | 1982-11-23 |
BE871748A (en) | 1979-05-03 |
AU4114478A (en) | 1980-05-01 |
DE2847833A1 (en) | 1979-05-10 |
FR2408247A1 (en) | 1979-06-01 |
FR2408247B1 (en) | 1984-03-09 |
GB2011229B (en) | 1982-08-11 |
DE2847833C2 (en) | 1986-01-09 |
JPS5474715A (en) | 1979-06-15 |
NL7810901A (en) | 1979-05-08 |
AU523034B2 (en) | 1982-07-08 |
AU8294782A (en) | 1982-09-02 |
CH647366A5 (en) | 1985-01-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |