JPS576423A - Demodulating circuit of mfm modulation signal - Google Patents

Demodulating circuit of mfm modulation signal

Info

Publication number
JPS576423A
JPS576423A JP8065580A JP8065580A JPS576423A JP S576423 A JPS576423 A JP S576423A JP 8065580 A JP8065580 A JP 8065580A JP 8065580 A JP8065580 A JP 8065580A JP S576423 A JPS576423 A JP S576423A
Authority
JP
Japan
Prior art keywords
circuit
pulse
signal
synchronizing
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8065580A
Other languages
Japanese (ja)
Other versions
JPS6260747B2 (en
Inventor
Toshiaki Hioki
Yoshihiko Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8065580A priority Critical patent/JPS576423A/en
Publication of JPS576423A publication Critical patent/JPS576423A/en
Publication of JPS6260747B2 publication Critical patent/JPS6260747B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To prevent propagation of a demodulation error of a data, by utilizing a PLL circuit again in accordance with a demodulation synchronizing signal, and demodulating a clock pulse, in a data and a synchronizing signal which have been demodulated by use of a PLL circuit. CONSTITUTION:An MFM signal which has been reproduced is inputted to an edge detecting pulse generating circuit 1, and an edge detecting pulse (c) synhronizing with an edge of the MFM signal is outputted from the circuit 1. This pulse (c) is inputted to a PLL circuit 2, a 101 pattern detecting circuit 5, and an FF circuit 4, and a demodulation synchronizing signal (j) is obtained from a synchronizing detecting circuit 6 of a demodulating circuit 7. The signal (j) is inputted to a PLL circuit 8, and a clock pulse (k) synchronizing with the signal (j) is obtained from the circuit 8. As far as this pulse (k) is concerned, a pulse (k) never goes out of order even if reproduction of a data falls into disorder during that time, if only synchronizing signal is reproduced exactly. Accordingly, when the pulse (k) is utilized, it is possible to obtain a demodulated data whose error is fewer than that of an FF circuit 12.
JP8065580A 1980-06-13 1980-06-13 Demodulating circuit of mfm modulation signal Granted JPS576423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8065580A JPS576423A (en) 1980-06-13 1980-06-13 Demodulating circuit of mfm modulation signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8065580A JPS576423A (en) 1980-06-13 1980-06-13 Demodulating circuit of mfm modulation signal

Publications (2)

Publication Number Publication Date
JPS576423A true JPS576423A (en) 1982-01-13
JPS6260747B2 JPS6260747B2 (en) 1987-12-17

Family

ID=13724366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8065580A Granted JPS576423A (en) 1980-06-13 1980-06-13 Demodulating circuit of mfm modulation signal

Country Status (1)

Country Link
JP (1) JPS576423A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934216U (en) * 1982-08-30 1984-03-02 リンナイ株式会社 Baking machine
WO1984003581A1 (en) * 1983-03-08 1984-09-13 Sony Corp Apparatus for reproducing data signal
JPS61120381A (en) * 1984-11-13 1986-06-07 デイジタル　イクイプメント　コーポレーシヨン Phase fixing loop for mfm data recording
JPS62252579A (en) * 1986-04-25 1987-11-04 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Restoration timing setting for pulse width modulation data
EP3422626A1 (en) * 2017-06-29 2019-01-02 Analog Devices, Inc. Demodulator for pulse-width modulated clock signals

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934216U (en) * 1982-08-30 1984-03-02 リンナイ株式会社 Baking machine
WO1984003581A1 (en) * 1983-03-08 1984-09-13 Sony Corp Apparatus for reproducing data signal
JPS61120381A (en) * 1984-11-13 1986-06-07 デイジタル　イクイプメント　コーポレーシヨン Phase fixing loop for mfm data recording
JPS62252579A (en) * 1986-04-25 1987-11-04 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Restoration timing setting for pulse width modulation data
EP3422626A1 (en) * 2017-06-29 2019-01-02 Analog Devices, Inc. Demodulator for pulse-width modulated clock signals
CN109217852A (en) * 2017-06-29 2019-01-15 美国亚德诺半导体公司 Demodulator for pulsewidth modulation clock signal
US10749717B2 (en) 2017-06-29 2020-08-18 Analog Devices, Inc. Demodulator for pulse-width modulated clock signals

Also Published As

Publication number Publication date
JPS6260747B2 (en) 1987-12-17

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