JPS5676853A - Program debug device - Google Patents

Program debug device

Info

Publication number
JPS5676853A
JPS5676853A JP15397279A JP15397279A JPS5676853A JP S5676853 A JPS5676853 A JP S5676853A JP 15397279 A JP15397279 A JP 15397279A JP 15397279 A JP15397279 A JP 15397279A JP S5676853 A JPS5676853 A JP S5676853A
Authority
JP
Japan
Prior art keywords
memory
external
mode
circuit
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15397279A
Other languages
Japanese (ja)
Inventor
Masao Yoshimura
Fuminobu Furukawa
Mineji Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP15397279A priority Critical patent/JPS5676853A/en
Publication of JPS5676853A publication Critical patent/JPS5676853A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To minimize the memory capacity of the external auxiliary memory less than the ROM and at the same time secure an easy control of the memory capacity at the site, by inhibiting the ROM within the CPU to select the external auxiliary memory in the mode under which the priority is given to the external memory.
CONSTITUTION: The address setting circuit 60 sets the range of address for the external auxiliary memory RAM51 which can read and write freely. Then the internal exclusive mode or the external exclusive mode is set by the memory mode setting switch 81 of the memory selection circuit 80. Thus in case the external priority mode is set, the ROM42 is inhibited when the address in the range set by the circuit 60 is designated. At the same time, the circuit 80 selects the external auxiliary memory 51. As a result, the memory capacity of the memory 51 can be set much less than the ROM42 and also is controlled easily at the site.
COPYRIGHT: (C)1981,JPO&Japio
JP15397279A 1979-11-27 1979-11-27 Program debug device Pending JPS5676853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15397279A JPS5676853A (en) 1979-11-27 1979-11-27 Program debug device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15397279A JPS5676853A (en) 1979-11-27 1979-11-27 Program debug device

Publications (1)

Publication Number Publication Date
JPS5676853A true JPS5676853A (en) 1981-06-24

Family

ID=15574095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15397279A Pending JPS5676853A (en) 1979-11-27 1979-11-27 Program debug device

Country Status (1)

Country Link
JP (1) JPS5676853A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819962A (en) * 1981-07-29 1983-02-05 Yokogawa Hokushin Electric Corp Microprocessor analyzer
JPH04332051A (en) * 1991-05-07 1992-11-19 Fuji Electric Co Ltd Program debugging system apparatus built-in type microcomputer
JPH05334071A (en) * 1992-05-28 1993-12-17 Matsushita Electric Ind Co Ltd One-chip microcomputer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5819962A (en) * 1981-07-29 1983-02-05 Yokogawa Hokushin Electric Corp Microprocessor analyzer
JPS6365982B2 (en) * 1981-07-29 1988-12-19 Yokogawa Electric Corp
JPH04332051A (en) * 1991-05-07 1992-11-19 Fuji Electric Co Ltd Program debugging system apparatus built-in type microcomputer
JPH05334071A (en) * 1992-05-28 1993-12-17 Matsushita Electric Ind Co Ltd One-chip microcomputer

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