JPS54109730A - Semiconductor read-only memory - Google Patents
Semiconductor read-only memoryInfo
- Publication number
- JPS54109730A JPS54109730A JP1648978A JP1648978A JPS54109730A JP S54109730 A JPS54109730 A JP S54109730A JP 1648978 A JP1648978 A JP 1648978A JP 1648978 A JP1648978 A JP 1648978A JP S54109730 A JPS54109730 A JP S54109730A
- Authority
- JP
- Japan
- Prior art keywords
- output
- precharge
- inverter
- detecting
- fetqs1
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
Landscapes
- Read Only Memory (AREA)
Abstract
PURPOSE:To increase the operation velocity with limitation of the precharge level for each output point by giving a common driving to plural units of precharge FET's with the output of the NOR gate which uses the inverter output and the inverse signal of the precharge clock as the two input. CONSTITUTION:Detecting FETQS1-QSn are connected in series in the same number as that corresponding to the number of the units of memory matrix groups MR1-MRn, and the output points of these matrix groups are connected to the gates of the detecting FET's. Then inverter TN1, which is controlled by the signal of the connection point between decoder precharging FETQPA and detecting FETQS1, is installed, and at the same time NOR gate circuit NRO is added using the output of the inverter and inverse signal phiB of precharge clock phiB as the two input. And the common driving is given to precharging FETQP1-QPn via the output of circuit NRO. Thus, the precharge level is controlled for each output point to increase the opertion velocity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1648978A JPS54109730A (en) | 1978-02-17 | 1978-02-17 | Semiconductor read-only memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1648978A JPS54109730A (en) | 1978-02-17 | 1978-02-17 | Semiconductor read-only memory |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60058373A Division JPS61105799A (en) | 1985-03-25 | 1985-03-25 | Semiconductor read only memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54109730A true JPS54109730A (en) | 1979-08-28 |
JPS6146919B2 JPS6146919B2 (en) | 1986-10-16 |
Family
ID=11917694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1648978A Granted JPS54109730A (en) | 1978-02-17 | 1978-02-17 | Semiconductor read-only memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54109730A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5637434U (en) * | 1979-08-31 | 1981-04-09 | ||
JPS5647996A (en) * | 1979-09-20 | 1981-04-30 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor memory device |
JPS59110095A (en) * | 1982-12-14 | 1984-06-25 | Sanyo Electric Co Ltd | Read-only memory |
-
1978
- 1978-02-17 JP JP1648978A patent/JPS54109730A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5637434U (en) * | 1979-08-31 | 1981-04-09 | ||
JPS5647996A (en) * | 1979-09-20 | 1981-04-30 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor memory device |
JPS59110095A (en) * | 1982-12-14 | 1984-06-25 | Sanyo Electric Co Ltd | Read-only memory |
Also Published As
Publication number | Publication date |
---|---|
JPS6146919B2 (en) | 1986-10-16 |
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