JPS54102926A - Memory control system for character display unit - Google Patents
Memory control system for character display unitInfo
- Publication number
- JPS54102926A JPS54102926A JP957978A JP957978A JPS54102926A JP S54102926 A JPS54102926 A JP S54102926A JP 957978 A JP957978 A JP 957978A JP 957978 A JP957978 A JP 957978A JP S54102926 A JPS54102926 A JP S54102926A
- Authority
- JP
- Japan
- Prior art keywords
- address
- signal
- counter
- case
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To reduce the number of types down to the minor types for general purpose and thus to realize the cost reduction through mass production by providing the switching circuit which selects selectively to contents between plural refresh memory groups and plural registers.
CONSTITUTION: The odd and even addresses of the received data are identified by the lowest bit of address counter 9 which indicates the writing address and then memorized into refresh memory group 1 in the case of the even address and into memory group 2 in the case of the odd address respectively. Then the bits other than the lowest one of refresh counter 10 are sent to address switching circuit 11, and then signal (a) is applied to group 1 and 2. At the same time, output signal (b) and (c) are memorized in register 3 and 4. The output os register 3 and 4 is put into character generator CG7 based on signal (e) which is controlled by lowest bit (d) of counter 10 and via switching timing circuit 6. Thus, the dot pattern is generated. The output of CG7 is turned to the serial signal through the parallel- series converter circuit to be video-displayed. In this case, reading period T2 is set longer than display time T1 to correct the delay of the memory.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP957978A JPS54102926A (en) | 1978-01-31 | 1978-01-31 | Memory control system for character display unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP957978A JPS54102926A (en) | 1978-01-31 | 1978-01-31 | Memory control system for character display unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54102926A true JPS54102926A (en) | 1979-08-13 |
Family
ID=11724211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP957978A Pending JPS54102926A (en) | 1978-01-31 | 1978-01-31 | Memory control system for character display unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54102926A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5880737A (en) * | 1981-10-20 | 1983-05-14 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Interactive text processing system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012936A (en) * | 1973-06-05 | 1975-02-10 | ||
| JPS5230123A (en) * | 1975-09-03 | 1977-03-07 | Oki Electric Ind Co Ltd | Time sharing using method of display memory |
-
1978
- 1978-01-31 JP JP957978A patent/JPS54102926A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5012936A (en) * | 1973-06-05 | 1975-02-10 | ||
| JPS5230123A (en) * | 1975-09-03 | 1977-03-07 | Oki Electric Ind Co Ltd | Time sharing using method of display memory |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5880737A (en) * | 1981-10-20 | 1983-05-14 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Interactive text processing system |
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