JPS5384534A - Refresh system for memory unit - Google Patents

Refresh system for memory unit

Info

Publication number
JPS5384534A
JPS5384534A JP16032476A JP16032476A JPS5384534A JP S5384534 A JPS5384534 A JP S5384534A JP 16032476 A JP16032476 A JP 16032476A JP 16032476 A JP16032476 A JP 16032476A JP S5384534 A JPS5384534 A JP S5384534A
Authority
JP
Japan
Prior art keywords
memory unit
refresh system
refresh
write
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16032476A
Other languages
Japanese (ja)
Inventor
Takashi Ibi
Takashi Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16032476A priority Critical patent/JPS5384534A/en
Publication of JPS5384534A publication Critical patent/JPS5384534A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To multiply the refresh distance by n and to increase the efficiency of usage for the memory unit, by performing the operation of one read/write in one memory cycle at normal read/write and the refresh operation of n times at refreshing.
JP16032476A 1976-12-29 1976-12-29 Refresh system for memory unit Pending JPS5384534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16032476A JPS5384534A (en) 1976-12-29 1976-12-29 Refresh system for memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16032476A JPS5384534A (en) 1976-12-29 1976-12-29 Refresh system for memory unit

Publications (1)

Publication Number Publication Date
JPS5384534A true JPS5384534A (en) 1978-07-26

Family

ID=15712489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16032476A Pending JPS5384534A (en) 1976-12-29 1976-12-29 Refresh system for memory unit

Country Status (1)

Country Link
JP (1) JPS5384534A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2523356A1 (en) * 1982-03-10 1983-09-16 Hitachi Ltd MOS DYNAMIC MEMORY WITH DIRECT ACCESS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2523356A1 (en) * 1982-03-10 1983-09-16 Hitachi Ltd MOS DYNAMIC MEMORY WITH DIRECT ACCESS

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