JPS5384534A - Refresh system for memory unit - Google Patents
Refresh system for memory unitInfo
- Publication number
- JPS5384534A JPS5384534A JP16032476A JP16032476A JPS5384534A JP S5384534 A JPS5384534 A JP S5384534A JP 16032476 A JP16032476 A JP 16032476A JP 16032476 A JP16032476 A JP 16032476A JP S5384534 A JPS5384534 A JP S5384534A
- Authority
- JP
- Japan
- Prior art keywords
- memory unit
- refresh system
- refresh
- write
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To multiply the refresh distance by n and to increase the efficiency of usage for the memory unit, by performing the operation of one read/write in one memory cycle at normal read/write and the refresh operation of n times at refreshing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16032476A JPS5384534A (en) | 1976-12-29 | 1976-12-29 | Refresh system for memory unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16032476A JPS5384534A (en) | 1976-12-29 | 1976-12-29 | Refresh system for memory unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5384534A true JPS5384534A (en) | 1978-07-26 |
Family
ID=15712489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16032476A Pending JPS5384534A (en) | 1976-12-29 | 1976-12-29 | Refresh system for memory unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5384534A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2523356A1 (en) * | 1982-03-10 | 1983-09-16 | Hitachi Ltd | MOS DYNAMIC MEMORY WITH DIRECT ACCESS |
-
1976
- 1976-12-29 JP JP16032476A patent/JPS5384534A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2523356A1 (en) * | 1982-03-10 | 1983-09-16 | Hitachi Ltd | MOS DYNAMIC MEMORY WITH DIRECT ACCESS |
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