JPS5427333A - Memory element - Google Patents

Memory element

Info

Publication number
JPS5427333A
JPS5427333A JP9272277A JP9272277A JPS5427333A JP S5427333 A JPS5427333 A JP S5427333A JP 9272277 A JP9272277 A JP 9272277A JP 9272277 A JP9272277 A JP 9272277A JP S5427333 A JPS5427333 A JP S5427333A
Authority
JP
Japan
Prior art keywords
memory element
memory unit
redece
piling
feeder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9272277A
Other languages
Japanese (ja)
Inventor
Nobuo Tsuda
Tomoyoshi Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9272277A priority Critical patent/JPS5427333A/en
Publication of JPS5427333A publication Critical patent/JPS5427333A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To redece the piling of the instantaneous current and then to avoid the potential variation of the feeder for the memory unit comprising plural memory units, by applying the refresh start or the read/write start to each memory unit with the sequential time lag.
JP9272277A 1977-08-02 1977-08-02 Memory element Pending JPS5427333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9272277A JPS5427333A (en) 1977-08-02 1977-08-02 Memory element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9272277A JPS5427333A (en) 1977-08-02 1977-08-02 Memory element

Publications (1)

Publication Number Publication Date
JPS5427333A true JPS5427333A (en) 1979-03-01

Family

ID=14062331

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9272277A Pending JPS5427333A (en) 1977-08-02 1977-08-02 Memory element

Country Status (1)

Country Link
JP (1) JPS5427333A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5451430A (en) * 1977-09-30 1979-04-23 Fujitsu Ltd Refresh control system of semiconductor memory unit
JPS5987695A (en) * 1982-11-11 1984-05-21 Toshiba Corp Semiconductor memory device
JPS59229789A (en) * 1983-05-09 1984-12-24 Fuji Xerox Co Ltd Refresh controller of dynamic memory
EP0165612A2 (en) * 1984-06-20 1985-12-27 Nec Corporation Memory circuit having a plurality of cell arrays
JPS6386193A (en) * 1986-09-29 1988-04-16 Mitsubishi Electric Corp Semiconductor storage device
JPH04324188A (en) * 1991-04-24 1992-11-13 Mitsubishi Electric Corp Dynamic ram controller circuit device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5297638A (en) * 1976-02-12 1977-08-16 Hitachi Ltd Refresh control system
JPS538529A (en) * 1976-07-13 1978-01-26 Toshiba Corp Refreshing method for semiconductor memory
JPS575759U (en) * 1980-06-05 1982-01-12

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5297638A (en) * 1976-02-12 1977-08-16 Hitachi Ltd Refresh control system
JPS538529A (en) * 1976-07-13 1978-01-26 Toshiba Corp Refreshing method for semiconductor memory
JPS575759U (en) * 1980-06-05 1982-01-12

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5451430A (en) * 1977-09-30 1979-04-23 Fujitsu Ltd Refresh control system of semiconductor memory unit
JPS5987695A (en) * 1982-11-11 1984-05-21 Toshiba Corp Semiconductor memory device
JPH053078B2 (en) * 1982-11-11 1993-01-13 Tokyo Shibaura Electric Co
JPS59229789A (en) * 1983-05-09 1984-12-24 Fuji Xerox Co Ltd Refresh controller of dynamic memory
EP0165612A2 (en) * 1984-06-20 1985-12-27 Nec Corporation Memory circuit having a plurality of cell arrays
JPS618796A (en) * 1984-06-20 1986-01-16 Nec Corp Dynamic memory
JPS6386193A (en) * 1986-09-29 1988-04-16 Mitsubishi Electric Corp Semiconductor storage device
JPH04324188A (en) * 1991-04-24 1992-11-13 Mitsubishi Electric Corp Dynamic ram controller circuit device

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