JPS5313875A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5313875A
JPS5313875A JP8857176A JP8857176A JPS5313875A JP S5313875 A JPS5313875 A JP S5313875A JP 8857176 A JP8857176 A JP 8857176A JP 8857176 A JP8857176 A JP 8857176A JP S5313875 A JPS5313875 A JP S5313875A
Authority
JP
Japan
Prior art keywords
semiconductor device
filming
gold
tin
metal foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8857176A
Other languages
Japanese (ja)
Inventor
Masao Hayakawa
Takamichi Maeda
Tadao Shinohara
Masao Kumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP8857176A priority Critical patent/JPS5313875A/en
Publication of JPS5313875A publication Critical patent/JPS5313875A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To perform bonding of high reliability by forming the chip bonding region of the conductor deposited on an insulation substrate through filming of tin and gold on the main metal foil film.
COPYRIGHT: (C)1978,JPO&Japio
JP8857176A 1976-07-23 1976-07-23 Semiconductor device Pending JPS5313875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8857176A JPS5313875A (en) 1976-07-23 1976-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8857176A JPS5313875A (en) 1976-07-23 1976-07-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5313875A true JPS5313875A (en) 1978-02-07

Family

ID=13946543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8857176A Pending JPS5313875A (en) 1976-07-23 1976-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5313875A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105144A (en) * 1993-07-27 1995-04-21 Internatl Business Mach Corp <Ibm> Stacking of circuited polymer dielectric panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105144A (en) * 1993-07-27 1995-04-21 Internatl Business Mach Corp <Ibm> Stacking of circuited polymer dielectric panel

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