JPS5054260A - - Google Patents
Info
- Publication number
- JPS5054260A JPS5054260A JP49047436A JP4743674A JPS5054260A JP S5054260 A JPS5054260 A JP S5054260A JP 49047436 A JP49047436 A JP 49047436A JP 4743674 A JP4743674 A JP 4743674A JP S5054260 A JPS5054260 A JP S5054260A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US360392A US3881173A (en) | 1973-05-14 | 1973-05-14 | Condition code determination and data processing |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5054260A true JPS5054260A (ja) | 1975-05-13 |
JPS5517976B2 JPS5517976B2 (ja) | 1980-05-15 |
Family
ID=23417778
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4743674A Expired JPS5517976B2 (ja) | 1973-05-14 | 1974-04-26 |
Country Status (2)
Country | Link |
---|---|
US (1) | US3881173A (ja) |
JP (1) | JPS5517976B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH023822A (ja) * | 1988-06-21 | 1990-01-09 | Matsushita Electric Ind Co Ltd | データ処理装置 |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5148937A (en) * | 1974-10-25 | 1976-04-27 | Fujitsu Ltd | Kiokusochi niokeru junjoseigyohoshiki |
JPS5848146A (ja) * | 1981-09-18 | 1983-03-22 | Toshiba Corp | 命令先取り方式 |
US4477872A (en) * | 1982-01-15 | 1984-10-16 | International Business Machines Corporation | Decode history table for conditional branch instructions |
JPS6015745A (ja) * | 1983-07-06 | 1985-01-26 | Nec Corp | 情報処理装置 |
US4578750A (en) * | 1983-08-24 | 1986-03-25 | Amdahl Corporation | Code determination using half-adder based operand comparator |
JPH0769818B2 (ja) * | 1984-10-31 | 1995-07-31 | 株式会社日立製作所 | デ−タ処理装置 |
US4747046A (en) * | 1985-06-28 | 1988-05-24 | Hewlett-Packard Company | Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch |
JPS62226232A (ja) * | 1986-03-28 | 1987-10-05 | Toshiba Corp | 分岐先アドレス算出回路 |
US4845659A (en) * | 1986-08-15 | 1989-07-04 | International Business Machines Corporation | Accelerated validity response permitting early issue of instructions dependent upon outcome of floating point operations |
US4841476A (en) * | 1986-10-06 | 1989-06-20 | International Business Machines Corporation | Extended floating point operations supporting emulation of source instruction execution |
US4967351A (en) * | 1986-10-17 | 1990-10-30 | Amdahl Corporation | Central processor architecture implementing deterministic early condition code analysis using digit based, subterm computation and selective subterm combination |
JP2723238B2 (ja) * | 1988-01-18 | 1998-03-09 | 株式会社東芝 | 情報処理装置 |
KR0136594B1 (ko) * | 1988-09-30 | 1998-10-01 | 미다 가쓰시게 | 단일칩 마이크로 컴퓨터 |
DE68927218T2 (de) * | 1988-10-18 | 1997-02-06 | Hewlett Packard Co | Verfahren und Vorrichtung für Zustandskode in einem Zentralprozessor |
EP0402524B1 (en) * | 1988-11-25 | 1996-10-02 | Nec Corporation | Microcomputer capable of quickly processing a branch instruction code |
CA2016068C (en) * | 1989-05-24 | 2000-04-04 | Robert W. Horst | Multiple instruction issue computer architecture |
US5255371A (en) * | 1990-04-02 | 1993-10-19 | Unisys Corporation | Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands |
US5872910A (en) * | 1996-12-27 | 1999-02-16 | Unisys Corporation | Parity-error injection system for an instruction processor |
US7546444B1 (en) | 1999-09-01 | 2009-06-09 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
WO2001016714A1 (en) | 1999-09-01 | 2001-03-08 | Intel Corporation | Fast write instruction for micro engine used in multithreaded parallel processor architecture |
US7681018B2 (en) | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
US7487505B2 (en) * | 2001-08-27 | 2009-02-03 | Intel Corporation | Multithreaded microprocessor with register allocation based on number of active threads |
US7216204B2 (en) | 2001-08-27 | 2007-05-08 | Intel Corporation | Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment |
US6868476B2 (en) | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
US7225281B2 (en) | 2001-08-27 | 2007-05-29 | Intel Corporation | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms |
US7610451B2 (en) * | 2002-01-25 | 2009-10-27 | Intel Corporation | Data transfer mechanism using unidirectional pull bus and push bus |
US7437724B2 (en) | 2002-04-03 | 2008-10-14 | Intel Corporation | Registers for data transfers |
US7337275B2 (en) * | 2002-08-13 | 2008-02-26 | Intel Corporation | Free list and ring data structure management |
US6941438B2 (en) | 2003-01-10 | 2005-09-06 | Intel Corporation | Memory interleaving |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3387278A (en) * | 1965-10-20 | 1968-06-04 | Bell Telephone Labor Inc | Data processor with simultaneous testing and indexing on conditional transfer operations |
US3418638A (en) * | 1966-09-21 | 1968-12-24 | Ibm | Instruction processing unit for program branches |
US3562713A (en) * | 1967-03-17 | 1971-02-09 | Burroughs Corp | Method and apparatus for establishing a branch communication in a digital computer |
US3577189A (en) * | 1969-01-15 | 1971-05-04 | Ibm | Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3629853A (en) * | 1959-06-30 | 1971-12-21 | Ibm | Data-processing element |
NL262931A (ja) * | 1960-03-29 | |||
US3544973A (en) * | 1968-03-13 | 1970-12-01 | Westinghouse Electric Corp | Variable structure computer |
-
1973
- 1973-05-14 US US360392A patent/US3881173A/en not_active Expired - Lifetime
-
1974
- 1974-04-26 JP JP4743674A patent/JPS5517976B2/ja not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3387278A (en) * | 1965-10-20 | 1968-06-04 | Bell Telephone Labor Inc | Data processor with simultaneous testing and indexing on conditional transfer operations |
US3418638A (en) * | 1966-09-21 | 1968-12-24 | Ibm | Instruction processing unit for program branches |
US3562713A (en) * | 1967-03-17 | 1971-02-09 | Burroughs Corp | Method and apparatus for establishing a branch communication in a digital computer |
US3577189A (en) * | 1969-01-15 | 1971-05-04 | Ibm | Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH023822A (ja) * | 1988-06-21 | 1990-01-09 | Matsushita Electric Ind Co Ltd | データ処理装置 |
Also Published As
Publication number | Publication date |
---|---|
JPS5517976B2 (ja) | 1980-05-15 |
US3881173A (en) | 1975-04-29 |